Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2001-03-26

2003-04-01

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000, C257S309000

Reexamination Certificate

active

06541337

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof. More particularly, the present invention relates to a semiconductor memory device having a memory cell array region and a peripheral circuit region, and to a manufacturing method thereof.
2. Description of the Background Art
Recently, because of widespread use of information equipments including computers, the demand for semiconductor memory devices has been rapidly increasing. As to the function, a memory device having large scale storage region and capable of high speed operation has been required. Accordingly, technical development has been made to attain higher degree of integration, high speed response and high reliability of the semiconductor memory device.
A DRAM (Dynamic Random Access Memory) has been generally known as one of the semiconductor memory devices which allows random input/output of memory information. The DRAM includes a memory array
51
which is a storage region for storing a large number of pieces of memory information, and a peripheral circuitry controlling the memory cells in the memory cell array
51
for external input/output, as shown in FIG.
45
.
The peripheral circuitry mainly includes a row and column address buffer
52
, a row decoder
53
, a column decoder
54
, a sense refresh amplifier
55
, a data in buffer
56
, a data out buffer
57
and a clock generator
58
.
On a semiconductor chip of the DRAM having such a structure, memory cell array
51
occupies a large area. A plurality of memory cells each for storing unit memory information are formed arranged in a matrix. The memory cell generally consists of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto, and is widely known as a one transistor, one capacitor type memory cell. The memory cell having such a simple structure facilitates improvement of the degree of integration of the memory cell array, and therefore it has been widely used for DRAMs having large capacity.
In such a DRAM, the conventional structure at an interface between the memory cell array region and the peripheral circuit region is as shown in
FIG. 46
, for example.
Referring to
FIG. 46
, a capacitor
105
constituting the memory cell has a cylindrical lower electrode (storage node)
101
, and an upper electrode (cell plate)
104
opposing to the lower electrode
101
with a capacitor dielectric film
103
interposed.
The lower electrode
101
is formed on an insulating layer
116
, and is electrically connected to a source/drain region (not shown) of the MOS transistor through a conductive layer
102
in a contact hole
118
. Further, an insulating layer
106
is formed to extend both to the memory cell array region and the peripheral circuit region, covering capacitor
105
.
In the structure of the conventional semiconductor memory device shown in
FIG. 46
, when the degree of integration is increased, a step or level difference S
2
between the memory cell array region and the peripheral circuit region increases, degrading process margin of the subsequent manufacturing steps. This problem will be described in detail in the following.
When higher degree of integration of the DRAM is promoted, the memory cell size is inevitably made smaller. As the memory cell size is reduced, two-dimensional area of occupation of the substrate is reduced accordingly. Therefore, the amount of charges stored in the capacitor (amount of charges stored in 1 bit of memory cell) decreases, so that the operation of the DRAM as a storage region becomes unstable, lowering reliability.
In order to prevent the unstable operation of the DRAM, it is necessary to increase the capacitor capacitance within the limited two-dimensional area of occupation. As means to increase capacitor capacitance, approaches such as {circle around (1)} marking thinner the capacitor dielectric film, {circle around (2)} enlargement of opposing area of the capacitor and {circle around (3)} increase in dielectric constant of the capacitor dielectric film have been studied.
The approach {circle around (1)}, that is, making thinner the capacitor dielectric film has already reached the limit as long as a silicon oxide film is generally used as the capacitor dielectric film. The approach {circle around (3)}, that is, increase in dielectric constant of the capacitor dielectric film has various problems unsolved, as it is necessary to employ a material of high dielectric constant as the capacitor dielectric film. Therefore, the approach {circle around (2)}, that is, enlargement of the opposing area of the capacitor has been widely adopted as the simplest method.
In approach {circle around (2)}, the capacitor capacitance can be increased by providing a cylindrical portion at lower electrode
101
and making higher the cylindrical portion, as shown in FIG.
46
.
When the height of the cylindrical portion of lower electrode
101
is made higher, the step S
2
between the memory cell array region and the peripheral circuit region becomes higher. The higher the step S
2
, the more residue will be left at the portion of the step S
2
at the time of patterning the conductive layer on insulating layer
106
, possibly resulting in a failure such as a short-circuit of the conductive layer because of this residue. Thus, the larger step S
2
decreases process margin of the subsequent manufacturing steps.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device and manufacturing method thereof which can reduce the step between the memory cell array region and the peripheral circuit region in a small number of manufacturing steps.
The semiconductor memory device in accordance with the present invention, which has a memory cell array region including a plurality of memory cells and a peripheral circuit region including elements controlling the memory cells, includes a cylindrical electrode and an insulating layer. The cylindrical electrode is contained in the memory cell, and has a porous cylindrical portion. The insulating layer is formed only in the peripheral circuit region to make less steep the step resulting from the provision of the cylindrical electrode.
In the semiconductor memory device in accordance with the present invention, the insulating layer is provided only in the peripheral circuit region, and therefore the step between the memory cell array region and the peripheral circuit region can be made less steep by the thickness of the insulating layer. Accordingly, degradation of the process margin in the subsequent manufacturing steps can be prevented.
In the semiconductor memory device described above, preferably, the insulating layer has an end surface positioned at an interface between the memory cell array region and the peripheral circuit region, with the end surface arranged facing an outer peripheral surface of the cylindrical electrode.
By such an arrangement of the insulating layer, the step generated by the cylindrical electrode can be made less steep.
In the semiconductor memory device described above, preferably, a first silicon nitride film is further provided, formed in the memory cell array region to be in contact with a lower surface of the cylindrical electrode.
Therefore, the first silicon nitride film acts as an etching stopper, facilitating control of etching.
In the above described semiconductor memory device, preferably, a semiconductor substrate having a conductive region on its main surface, a second insulating layer having a contact hole formed on the main surface and reaching the conductive region, and a second silicon nitride film formed in contact with a side surface of the contact hole are further provided. The cylindrical electrode is electrically connected to the conductive region through the contact hole.
Accordingly, good electrical connection can be established between the cylindrical electrode and the conductive region.
In the above described semiconductor memory device, preferably, another electrode is further provi

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