Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-06-17
2003-03-25
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S230030, C365S094000
Reexamination Certificate
active
06538943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to semiconductor memories and, more particularly, to precharging in read-only memories.
2. Description of the Related Art
Read-only memories (ROMs) are a basic building block in integrated circuit design. As the name implies, ROMs are memories which can be read but not written. They are useful for storing a variety of constants which may be needed during operation of the integrated circuits, and may also store instructions for execution in a processor. For example, microcode used to execute complex instructions may be stored in a ROM. Additionally, in processors such as digital signal processors (DSPs), microcontrollers, and embedded processors, the program code to be executed may be stored in an ROM. The ROMs may be either integrated into the integrated circuit using the ROM contents or may be a separate chip coupled to the integrated circuit.
Generally, ROMs are arranged as a plurality of locations, each containing one or more bits. Each location is addressable in the ROM using a different address. Each location may include a transistor for each bit, either coupled or not coupled to a bitline used to output that bit. The bitline is precharged prior to activating the transistor. When the transistor is activated, if it is coupled to the bitline, the precharge is dissipated and one value (binary one or zero) for the bit is provided as the output. If the transistor is not coupled to the bitline, the precharge is not dissipated and the other value (binary zero or one) is provided as the output.
Some ROMs may be partitioned, in which the memory is divided into two or more partitions. One location in each partition may be mapped to a particular address presented to an address decoder in the ROM. However, only one of the partitions may output a value in response to a given read of the ROM.
For partitioned ROMs, precharging all of the partitions may lead to unnecessary power dissipation since the output of only one of the partitions is actually going to be selected as an output of the ROM for a given read.
SUMMARY OF THE INVENTION
A ROM described herein may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. The power dissipated precharging the partitions not to be read may be saved. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage.
The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM. The output circuit may not require a selection control in such embodiments. While a ROM is used in certain embodiments, other embodiments may be any type of memory, as desired.
Broadly speaking, an apparatus is contemplated, comprising a first partition of a memory array, a second partition of the memory array, and a precharge circuit. The first partition is configured to output at least a first signal on a first conductor, and the second partition is configured to output at least a second signal on a second conductor. Coupled to the first conductor and the second conductor, the precharge circuit is configured to precharge the first conductor to a voltage representing a binary value responsive to an input indicating that the first partition is selected for a read. Additionally, the precharge circuit is configured to not precharge the second conductor responsive to the input.
Additionally, a method is contemplated. A first partition of a memory array is selected for a read. A first conductor is precharged to a voltage representing a binary value responsive to selecting the first partition, wherein the first conductor corresponds to the first partition. Additionally, a second conductor corresponding to a second partition of the memory array is not precharged responsive to selecting the first partition.
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Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen Tan T.
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