Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1999-12-30
2003-09-30
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S600000, C711S167000, C710S005000
Reexamination Certificate
active
06629253
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of managing memory access requests from video overlay data streams.
BACKGROUND OF THE INVENTION
An important function of computer systems is that of processing isochronous data streams. Isochronous data streams are those data streams that have strict throughput and latency requirements. An example of one such data stream is a stream of overlay data for a graphics controller. If the required overlay data is not delivered to the graphics controller at the required rate and within the required time period, then some form of display corruption will result.
Isochronous data streams typically have very even data consumption rates, that is, for a given period of time, the amount of data consumed will always be the same. Memory access, on the other hand, is typically very uneven due to arbitration with other data streams. For example, when a graphics device requires data it must arbitrate for access to memory with other system resources. The result is uneven and unpredictable access to memory. Another issue with isochronous data streams is that an isochronous data stream is likely to operate at a different clock frequency than that of the memory subsystem. These two issues can be solved by using an intermediate storage first-in, first-out buffer (FIFO). The FIFO can accept data from memory at whatever rate the memory can deliver the data and the FIFO can output data at the rate required by the isochronous data stream.
The FIFO technique works so long as the FIFO is never allowed to go empty. If the FIFO goes empty at any point, the isochronous data stream will be corrupted. To help prevent this situation, isochronous data streams are typically assigned the highest priority for arbitrating access to memory. Overlay data streams present a problem in that overlay data streams may request an entire display line worth of data at a given time. Because isochronous data streams are typically assigned the highest arbitration priority, the overlay data stream can effectively shut out other data streams from accessing memory for significant periods of time during overlay data line transfers. Because the overlay display line can be quite large, a significant degradation of system performance can result. This may be especially true in the case where the overlay data is stored in system main memory, where the system's processor must compete for access to system main memory with the overlay data stream.
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Meinerth Kim
Sreenivas Aditya
Witter Todd M.
Cao Chun
Lee Thomas
Wells Calvin E.
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