Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-20
2003-07-15
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S727000
Reexamination Certificate
active
06594802
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
The present invention relates to apparatus and methods for accessing electrical nodes of electronic circuits for programming, testing, or debugging purposes.
One way of providing access to electrical nodes of Integrated Circuits (ICs) is commonly referred to as “scan testing,” which typically involves serially shifting digital data into state elements included in an IC to apply logic levels to selected nodes as test stimuli, and serially shifting digital date out of the state elements to capture logic levels generated at other nodes in response to the test stimuli. Such control and observation of an IC's electrical nodes via state elements is also used to provide “visibility” into an IC for debugging purposes. Further, an IC that supports scan testing is frequently used to access electrical nodes of other electronic circuits connected thereto. For example, these other electronic circuits may be embedded within the IC, i.e., embedded memories or cores, or externally connected to the IC.
Scan testing is typically performed in accordance with the IEEE 1149.1 Standard described in the IEEE 149.1-1990 Standard Test Access Port and Boundary Scan Architecture specification, the entire disclosure of which is incorporated herein by reference. The IEEE 1149.1 Standard was primarily developed to solve problems related to Printed Circuit Board (PCB) testing. The IEEE 1149.1 Standard is also typically used to access “scan chains” within ICs to facilitate testing and debugging of ICs, PCBs, and systems.
“Boundary scan” is an application of scan testing at input and output (I/O) pins of an IC to provide direct control and observation of electrical nodes using boundary scan operations. Boundary scan involves a specific type of scan path having a boundary scan register cell at each I/O pin of an IC. For example, by performing boundary scan operations, known logic levels may be placed directly on outputs of one circuit and observed at inputs of another circuit connected thereto. Boundary scan therefore provides a way of determining whether circuits are properly connected to each other on, e. g., a PCB, and/or whether there are manufacturing defects on the PCB that may prevent the circuits from carrying out their intended mission. Boundary scan tests can detect different types of defects on a PCB, e.g., broken circuit traces, cold solder joints, solder bridges, and electrostatic-discharge (ESD) induced failures in IC buffers.
FIG. 1
depicts boundary scan architecture
100
, which is compliant with the IEEE 1149.1 Standard and may be embedded in an IC to provide direct control and observation of electrical nodes via the IC's I/O pins. As depicted in
FIG. 1
, an IC compliant with the IEEE 1149.1 Standard includes the following four (4) mandatory pins: TDI, TDO, TCK, and TMS. Further, the IC optionally includes the pin, TRSTN. These pins, TDI, TDO, TCK, TMS, and optionally TRSTN, are commonly known as the Test Access Port (TAP).
In addition, the IC includes three (3) mandatory scan registers, i.e., an Instruction Register (IR)
104
; and, two (2) Data Registers (DRs), i.e., a Boundary Scan Register (BSR)
106
and a Bypass Register (BYPASS)
108
. Further, the IC optionally includes at least one User DR, i.e., a User DR
110
, which may be used to implement tests such as internal scan path testing and Built-In Self-Test. (BIST). Moreover, the IC includes a protocol interface
102
known as a TAP Controller, which includes a 16-state Finite State Machine (FSM) operated by the mandatory TMS and TCK input pins and other logic.
FIG. 3
depicts a state diagram
300
for the standard FSM of the Tap Controller
102
. A logic level on the TMS pins determines a next state of the FSM, and a clock signal on the TCK pin causes state transitions to occur. Further, an updated IR instruction selects the IR
104
, the BSR
106
, the BYPASS DR
108
, or the USER DR
110
for scan operations. Moreover, the FSM includes a Select-DR branch
301
that defines states for performing a “DR-scan” operation and a Select-IR branch
303
that defines states for performing an “IR-scan” operation.
The IR
104
, the BSR DR
106
, the BYPASS DR
108
, and the USER DR
110
each comprise a separate scan path; and, the TAP Controller
102
enables operation of only one of these scan registers at a time. The selected scan register shifts its scan data between the TDI pin and the TDO pin during a Shift-IR
324
state or a Shift-DR
310
state. Further, the selected scan register for the next set of scan operations is determined by the IR instruction that was previously updated in the IR
104
during an Update-IR
332
state. Moreover, the IEEE 1149.1 Standard uses both edges of the clock signal on the TCK pin. Specifically, a logic level on the TMS pin and scan data on the TDI pin are sampled on the rising edge of the clock signal, and scan data on the TDO pin changes on the falling edge of the clock signal.
The state diagram
300
of
FIG. 3
includes six (6) “steady-states,” i.e., a Test-Logic-Reset
302
state, a Run-Test/Idle
304
state, a Shift-DR
310
state, a Pause-DR
314
state, a Shift-IR
324
state, and a Pause-IR
328
state. According to the IEEE 1149.1 Standard, there is only one (1) steady-state when the TMS pin is set to logical 1, i.e., the Test-Logic-Reset
302
state; and, the FSM of the TAP Controller
102
can be reset (i.e., transition to the Test-Logic-Reset
302
state) within five (5) TCK clock signal transitions while the TMS pin is set to logical 1. The optional TRSTN pin provides another way to reset the FSM of the TAP Controller
102
. For example, setting the TRSTN pin to logical 0 causes an asynchronous reset of the TAP Controller
102
FSM.
The DR branch
301
and the IR branch
303
of the TAP Controller
102
FSM each includes six (6) states. Specifically, a Capture state, e.g., a Capture-DR
308
state and a Capture-IR
322
state, causes a selected scan register to capture data via parallel inputs of the scan register. This captured data is shifted out of the selected register on the TDO pin during the Shift-DR
310
state or the Shift-IR
324
state, while new scan data is simultaneously shifted into the register via the TDI pin.
After the scan shift operation is completed, new scan data is updated into a parallel update stage of the scan register. An IR or DR update operation is enabled upon entering either the Update-IR
332
state or the Update-DR state
318
, respectively.
A state sequence including an Exit
1
-DR
312
state, immediately followed by a Pause-DR
314
state, and immediately followed by an Exit
2
-DR
316
state is used to terminate or suspend the Shift-DR
310
state operation. Similarly, a state sequence including an Exit
1
-IR
326
state, immediately followed by a Pause-IR
328
state, and immediately followed by an Exit
2
-IR
330
state is used to terminate or suspend the Shift-IR
324
state operation. The Pause-DR
314
state and the Pause-IR
328
state are included in the TAP Controller
102
FSM primarily to account for potentially slow tester hardware and/or software performance.
The instructions updated in the IR
104
not only select scan registers for shifting scan data, but also determine test behavior, e.g., for boundary scan testing of PCB interconnects. The IEEE 1149.1 Standard specifies three (3) mandatory instructions and their corresponding test behavior. One such instruction is the BYPASS instruction, which selects the BYPASS DR
108
to provide a 1-bit scan path between TDI and TDO. For example, scan paths of multiple circuits compliant with the IEEE 1149.1 Standard may be chained together by serially connecting their respective TDI and TDO pins. The BYPASS instruction may then be used to “bypass” these potentially long scan paths when DRs corresponding thereto do not have to be accessed for particular test or debug operations. In this way, the BYPASS instruction(s) may be used to reduce the number of scan bits that are shifted.
Other mandatory i
Clark Christopher J.
Dervisoglu Bulent I.
Ricchetti Michael
Dinh Paul
Intellitech Corporation
LandOfFree
Method and apparatus for providing optimized access to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for providing optimized access to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing optimized access to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3046953