Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-05
2003-09-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C324S754090, C324S761010, C365S201000
Reexamination Certificate
active
06629282
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to a module based semiconductor test system which accommodates a combination of different types of test apparatuses of modular structure so as to easily create a desired type of semiconductor test system. Further, in the semiconductor test system of the present invention, a small number of high speed high performance test apparatuses (tester modules) and a large number low speed low performance test apparatuses (tester modules) are freely combined, thereby establishing a low cost test system. In the semiconductor test system of the present invention, the tester module and a tester board used in the tester module are configured as an event based tester to generate event based test patterns for testing a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
FIG. 1
is a schematic block diagram showing an example of a semiconductor test system in the conventional technology for testing a semiconductor integrated circuit (hereafter may also be referred to as “IC device”, “LSI under test” or “device under test”).
In the example of
FIG. 1
, a test processor
11
is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
, and the test pattern is supplied to a device under test (DUT)
19
through a driver
15
.
A response signal from the DUT
19
resulted from the test pattern is converted to a logic signal by an analog comparator
16
with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator
12
by a logic comparator
17
. The result of the logic comparison is stored in a failure memory
18
corresponding to the address of the DUT
19
. The driver
15
, the analog comparator
16
and switches (not shown) for changing pins of the device under test, are provided in a pin electronics
20
.
The circuit configuration noted above is provided to each test pin of the semiconductor test system. Therefore, since a large scale semiconductor test system has a large number of test pins, such as from 256 to 1048 test pins, and the same number of circuit configurations, each being shown in
FIG. 1
are incorporated, an actual semiconductor test system becomes a very large system.
FIG. 2
shows an example of outer appearance of such a semiconductor test system. The semiconductor test system is basically formed with a main frame
22
, a test head
24
, and a work station
26
.
The work station
26
is a computer provided with, for example, a graphic user interface (GUI) to function as an interface between the test system and a user. Operations of the test system, creation of test programs, and execution of the test programs are conducted through the work station
26
. The main frame
22
includes a large number of test channels each having the test processor
11
, pattern generator
12
, timing generator
13
, wave formatter
14
and comparator
17
shown in
FIG. 1
corresponding to the test pins.
The test head
24
includes a large number of printed circuit boards each having the pin electronics
20
shown in FIG.
1
. The test head
24
has, for example, a cylindrical shape in which the printed circuit boards forming the pin electronics are radially aligned. On an upper surface of the test head
24
, a device under test
19
is inserted in a test socket at about the center of a performance board
28
.
Between the pin electronics circuit and the performance board
28
, a pin (test) fixture
27
is provided which is a contact mechanism for communication of electrical signals. The pin fixture
27
includes a large number of contactors such as pogo-pins for electrically connecting the pin electronics circuits and the performance board. The device under test
19
receives a test pattern signal from the pin electronics and produces a response output signal.
In the conventional semiconductor test system, for producing a test pattern to be applied to a device under test, the test data which is described in, what is called a cycle based format, has been used. In the cycle based format, each variable in the test pattern is defined relative to each test cycle (tester rate) of the semiconductor test system. More specifically, test cycle (tester rate) descriptions, waveform (kinds of waveform and edge timings) descriptions, and vector descriptions in the test data specify the test pattern in a particular test cycle.
In the design stage of the device under test, under a computer aided design (CAD) environment, the resultant design data is evaluated by performing a logic simulation process through a test bench. However, the design evaluation data thus obtained through the test bench is described in an event based format. In the event based format, each change point (event) in a particular test pattern, such as from “0” to “1” or from “1” to “0”, is described with reference to a time passage. The time passage is expressed by, for example, an absolute time length from a predetermined reference point or a relative time length between two adjacent events.
The inventors of this invention have disclosed the comparison between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format in the U.S. patent application Ser. No. 09/340,371. The inventors of this invention have also proposed an event based test system as a semiconductor test system as a new concept test system. The details of the structure and operation of the event based test system is given in the U.S. patent application Ser. No. 09/406,300, now U.S. Pat. No. 6,532,561 owned by the same assignee of this invention.
As described in the foregoing, in the semiconductor test system, a large number of printed circuit boards and the like which is equal to or greater than the number of the test pins are provided, resulting in a very large system as a whole. In the conventional semiconductor test system, the printed circuit boards and the like are identical to one another.
For example, in a high speed and high resolution test system, such as a test rate of 500 MHz and timing accuracy of 80 picosecond, the printed circuit boards for all the test pins have the same capabilities, each being able to satisfy the test rate and timing accuracy. Thus, the conventional semiconductor test system inevitably becomes a high cost system. Further, since the identical circuit structure is used in each test pin, the test system can conduct only limited types of test.
However, in an actual device under test, almost always, not all of the pins of such a device under test require the highest performance of the semiconductor test system. For example, in a typical logic LSI device to be tested having several hundred pins, only several pins actually operate at the highest speed and thus require the highest speed test signal while other several hundred pins operate at substantially lower speeds and thus low speed test signals are sufficient to these pins. This is also true to a system-on-a-chip (SoC), a recent semiconductor device which draws high attention in the industry. Thus, high speed test signals are needed to only a small number of pins of an SoC while low speed test signals are sufficient for other pins.
In the conventional semiconductor test system, the high test performance which is needed only for a small number of pins of the device under test is equipped to all of the test pins, resulting in the cost increase of the test system. Further, because the conventional semiconductor t
Rajsuman Rochit
Sugamori Shigeru
Advantest Corp.
Britt Cynthia
Muramatsu & Associates
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