Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-21
2003-03-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S729000, C714S738000, C714S733000, C714S726000
Reexamination Certificate
active
06532571
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital logic design and testability of semiconductor chips and, more particularly, to a method to improve random pattern testability (RPT) analysis of a hierarchical design of a semiconductor chip.
2. Discussion of the Related Art
Random pattern testability of semiconductor chips has become increasingly important due to the emphasis on chip built-in self-test methods (BIST). BIST is a way of testing chip logic without the use of an external tester as disclosed in P. H. Bardell and W. H. McAnney, “Self-Testing of Multichip Modules,” Proceedings of the IEEE International Test Conference, 1982, pp. 200-204, which is hereby incorporated by reference. Once a chip is manufactured, it is subjected to electronic testing to verify that it works properly. BIST is increasingly an important part of this testing since less complex testers are required and perhaps no tester is required. After the semiconductor chip is assembled in a more complex system (a multi-chip circuit board, for example), BIST is often automatically run whenever the chip is first turned on. It may also be run during diagnostic or trouble-shooting routines. In many cases, BIST is the only test that may be run on a chip once it is installed in a more complex system like a multi-chip circuit board. The quality of the circuit board test is, therefore, heavily dependent on the quality of the BIST test, since there may be many semiconductor chips on the circuit board itself, each testable only by BIST at the assembly level.
Most BIST techniques use a pseudo-random pattern generator (PRPG) to generate test patterns. The PRPG is an internal logic circuit in the semiconductor chip itself that generates a random, but repeatable set of 1s and 0s that are applied to chip inputs and latches. E. B. Eichelberger, E. Lindbloom, J. A. Waicukauski, T. W. Williams, “Structured Logic Testing”, pp. 90-103, Prentice Hall, 1991. An exemplary way of applying PRPG data to latches is through a scan chain. E. B. Eichelberger and T. W. Williams, “A Logic Design Structure For LSI Testability,” Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462-468 describes such a scan technique, which is hereby incorporated by reference. In its most common implementation, the probability of a 1 at a latch or input equals the probability of a 0 =0.5 (i.e., P(0)=P(1)=0.5).
In general, it is not possible to test all logic on a semiconductor chip using BIST. One of the most common reasons for this is that certain logic structures are generally random pattern resistant. For example, the 32-input AND circuit
10
, shown in
FIG. 1
, is random pattern resistant. The 32-input AND circuit
10
includes a first 16-input AND circuit
12
and a second 16-input AND circuit
14
each fed to a separate AND gate
16
. Each AND circuit
12
and
14
also include a plurality of individual AND gates
18
. All AND inputs
20
are assumed to be controllable (fed directly by latches), and the output
22
of AND gate
16
is assumed to be the only observable point (directly feeds a latch). In order to test for single stuck-at faults on any one of the blocks in the first level, the 32-inputs
20
have to be specified with 31-inputs
20
at “1” to propagate a potential fault to the observable point or output
22
. In other words, should 31 inputs
20
be forced to a “1” and one input
20
be forced to a “0” if the circuit
10
is operating correctly, a “0” should be observed at the output
22
. If the circuit
10
is not operating properly, a fault or a “1” would be observed at the output
22
.
The probability of 31-inputs
20
being a “1” and one of the inputs
20
being a “0” randomly occurring in any single pattern is ½
32
. This probability is basically 0 for any practical test time. Methods exist that analyze logic for random pattern testability (RPT) and suggest test points that can improve the RPT. These methods are discussed in Sunil K. Jain and Vishwani D. Agrawal (AT & T Bell Laboratories), “Statistical Fault Analysis,” IEEE Design and Test of Computers, Vol 2, No. 2, February 1985, pp. 38-44; S. K. Jain and Vishwani D. Agrawal, “STAFAN: An Alternative To Fault Simulation,” ACM/IEEE 21st Design Automation Conference Proceedings, June 1984, pp. 18-23; and U.S. Pat. No. 3,761,695, each of which are hereby incorporated by reference.
A more testable version of the 32-input AND circuit
10
′, is shown in FIG.
2
. In this regard, like reference numerals will be used to identify like structures with respect to the 32-input AND circuit
10
, shown in FIG.
1
. As shown in
FIG. 2
, four test points
24
, using observation latches
26
(i.e., two in each 16-input AND circuits
12
and
14
) have been added to the design. Each observation latch
26
is based upon level sensitive scan design (LSSD) and includes a pair of master-slave latches which enables and provides observable and controllable points
24
. LSSD is further disclosed in detail in E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability,” Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462-468, which is hereby incorporated by reference.
In order to test the test points
24
, now only 8-inputs
20
must be specified. The one under test (i.e., “0”) and the next 7-inputs
20
set to a “1”. The probability of this result randomly occurring in any single pattern is ½
8
. This is only {fraction (1/256)}. Since generally tens of thousands of patterns are applied, this is now easily testable. In fact, with this configuration, all but three AND gates are testable. In this regard, the last AND gates
18
in circuits
12
and
14
and the AND gate
16
are not testable. Therefore, the circuits in these last two stages may still have some faults (input stuck at 0, for example), which are not testable as shown in FIG.
2
.
In order to test these last two stages, additional test points, generally known as control test points, must be added to the circuit
10
′. These additional test points are shown in FIG.
3
. Here again, like reference numerals will be used to identify like structures with respect to the circuit
10
″. As shown in
FIG. 3
, two control latches
28
are added to each circuit
12
and
14
which again comprise a pair of master and slave latches. A pair of two way OR gates
30
are also added to each circuit
12
and
14
. The addition of the control latches
28
and the OR gates
30
enables an alternate way to set an input/output to a “1” state. In this regard, in order to test the final AND gate
16
for a stuck-at-0 fault on either input, both inputs must be set to a “1”.
In the 32-way AND circuits
10
and
10
′, shown in
FIGS. 1 and 2
, the 32-inputs
20
have to be set to “1”. This is not possible with random patterns. In the 32-way AND circuit
10
″ of
FIG. 3
, the states of only four control latches
28
need to be specified, which is easily tested with random patterns. In other words, upon setting the control latches
28
to a “1” state, each two-way OR
30
will be forced to have a “1” output, thereby causing the last AND gates
18
in circuits
12
and
14
to provide “1” inputs to the AND gate
16
to confirm the operation of the entire circuit
10
″. This modified 32-input AND circuit
10
″ is one hundred percent (100%) random pattern testable based upon the addition of the observation latches
26
, the control latches
28
and the OR gates
30
. However, one disadvantage with this circuit
10
″ is that the OR gates
30
are placed in-line with each circuit
12
and
14
, thus causing these circuits
12
and
14
to run slower than if the OR gates
30
were not present.
A flow chart illustrating a typical prior art random pattern testability analysis or process
32
is shown in FIG.
4
. The RPT analysis
32
receives an input from a design netlist input block
34
. The design netlist block
34
identifies the circuit or entity being analyzed an
Gabrielson Richard M.
McCauley Kevin W.
Rizzolo Richard F.
Robbins Bryan J.
Swenton Joseph M.
Augspurger Lynn L.
Dimyan Magid Y
Siek Vuthe
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