Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-11
2003-04-01
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S586000, C438S624000, C438S629000
Reexamination Certificate
active
06541333
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and to a technique for the manufacture thereof, and, more particularly, the invention relates to a technique which is effective for application to a dynamic random access memory (DRAM) requiring a storage holding operation, and which is suitable for high integration.
DRAMs are commonly classified as a trench type or a stacked type relative to their basic structures. The trench type is one wherein information storage capacitative elements (capacitors) are formed inside trenches defined in a substrate, whereas the stacked type is one wherein information storage capacitative elements are formed above transfer transistors (memory cell selection MISFETs (Metal Insulator Semiconductor Field Effect Transistors)) on the surface of a substrate. The stacked type is further classified into a CUB (Capacitor Under Bit-line) type wherein information storage capacitative elements are placed below bit lines and a COB Capacitor Over Bit-line) type wherein they are placed thereabove. Products of 64 Mbits or more, which currently are being mass produced, are respectively of the stacked type and are characterized by excellent reduction of the cell area. The COB type is becoming a mainstream device.
A structure of a DRAM having COB type memory cells is as follows.
Namely, the memory cells of the DRAM having the COB type memory cells are respectively placed at points where a plurality of word lines intersect with a plurality of bit lines disposed over a main or principal surface of a semiconductor substrate in matrix form. Each memory cell comprises one memory cell selection MISFET and one information storage capacitative element electrically directly connected to it. The memory cell selection MISFET is formed in an active area or region whose periphery is surrounded by device or element separation regions, and principally comprises a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is placed above the memory cell selection MISFET and is electrically connected to one of a source and drain shared between adjacent memory cell selection MISFETs aligned in the direction in which the memory cell selection MISFET extends. The information storage capacitative element is similarly placed above the memory cell selection MISFET and is electrically connected to the other of the source and drain. In order to replenish a reduction in the stored amount of electrical charge (Cs) of each information storage capacitative element, incident to a micro-fabrication of each memory cell, a lower electrode (storage electrode) of the information storage capacitative element placed above the bit line is processed into cylindrical form to thereby increase its surface area, and a capacitive insulating film and an upper electrode (plate electrode) are formed thereabove.
SUMMARY OF THE INVENTION
If the area of each memory cell of the conventional DRAM is designed so as to take up a minimum space, it is then necessary to form connecting hole (hereinafter called capacitive-electrode connecting hole) patterns for connecting the lower electrodes of the information storage capacitative elements to the active regions or the connecting plugs on the active regions and bit line patterns in minimum processing sizes. However, a large problem occurs in terms of their processing in order to form these patterns in the minimum processing sizes. This will be explained below with reference to the drawings.
FIG. 72
is a cross-sectional view for describing the problem on the processing of each capacitive-electrode connecting hole and shows a cross section of a memory cell portion as seen in the direction orthogonal to the direction in which each bit line extends.
Namely, when each memory cell of a DRAM includes an active region
203
surrounded by separation areas or regions
202
of a main or principal surface of a semiconductor substrate
201
, a semiconductor region
204
which is formed over the active region
203
and serves as the source and drain of a memory cell selection MISFET, a connecting plug
205
formed over the semiconductor region
204
, an information storage capacitative element C formed over the active region
203
and composed of an upper electrode
206
, a capacitive insulating film
207
and a lower electrode
208
, and a bit line
209
formed between the connecting plug
205
and the information storage capacitative element C as shown in FIG.
72
(
a
). It is necessary to form the active region
203
, the bit line
209
, and the capacitive-electrode connecting hole
210
for connecting the connecting plug
205
and the lower electrode
208
in minimum processing sizes for the purpose of forming each memory cell of the DRAM in a minimum processing size. However, a margin
211
for alignment with the bit line
209
at the processing of the capacitive-electrode connecting hole
210
cannot be ensured sufficiently. Therefore, there is a possibility that the lower electrode
208
and the bit line
209
will be short-circuited due to a displacement in alignment or a variation in processing size. As a result, the probability that a reduction in manufacturing yield will occur, increases.
To avoid such a problem, there is provided a method of effecting the processing of the capacitive-electrode connecting hole
210
on the bit line
209
on a self-alignment basis. This is a method of covering an upper portion of each bit line
209
with a silicon nitride film
212
, protecting the sides of the bit line
209
with sidewall spacers
213
composed of the silicon nitride film, controlling or adjusting etching conditions upon etching of silicon oxide films
214
and
215
by patterns for the capacitive-electrode connecting holes
210
to set a selection ratio of the silicon nitride film to each silicon oxide film sufficiently high, thereby etching only the silicon oxide films without cutting away the silicon nitride film so as to prevent the exposure of each bit line
209
, as shown in FIG.
72
(
b
). According to the method, even if an alignment displacement occurs in the pattern for each capacitive-electrode connecting hole
210
, the lower electrode
208
and the bit line
209
can be prevented from being short-circuited.
In the present structure, however, the thickness of the silicon nitride film
212
is required in addition to the thickness of the bit line
209
and the thickness from the connecting plug
205
to the surface of the silicon oxide film
214
increases, as shown in FIG.
72
(
b
). Therefore, a new problem arises in that the height
216
up to the information storage capacitative element C increases and hence the height of each cell itself becomes high, thereby increasing a step-like offset between the cell and a peripheral circuit region.
An object of the present invention is to provide a technique which is capable of reducing the width of a bit line beyond a processing limit of photolithography.
Another object of the present invention is to provide a structure of a semiconductor integrated circuit device which is capable of preventing short circuits in a bit line and a lower electrode of an information storage capacitive element without increasing the height of a memory cell, and a method of manufacturing the same.
A further object of the present invention is to provide a technique which is capable of reducing the capacitance of a bit line and to provide a semiconductor integrated circuit device which is high in detection sensitivity and excellent in noise resistance.
A still further object of the present invention is to provide a structure of a semiconductor integrated circuit device, which adopts simple flat or plane patterns suitable for photolithography and a technique capable of improving the processing margin.
A still further object of the present invention is to provide a structure of a semiconductor integrated circuit device which is suitable for high integration of a DRAM and a method of manufactu
Kuroda Kenichi
Shukuri Shoji
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Quach T. N.
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