Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2001-01-26
2003-09-02
Valentine, Donald R. (Department: 1742)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S22400M, C204S22400M, C204S267000, C204S275100, C204S276000, C204S297010, C204S297140
Reexamination Certificate
active
06613200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for deposition and planarization of a material, such as a metal, on a substrate.
2. Background of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electro-chemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical polishing composition, typically a slurry or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing material in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing material. Relative motion is then provided between the polishing material and the substrate while dispersing the polishing composition therebetween. The combined chemical and mechanical activity causes a controlled removal of material from the surface of the substrate, resulting in a generally planar substrate surface.
Copper is becoming a metal of choice in ULSI to form interconnects that provide conductive pathways in integrated circuits and other electronic devices. Copper is a material having advantageous properties such as lower resistance compared to traditionally used materials such as aluminum. Copper can be deposited by various techniques such as PVD, CVD and electroplating. Electroplating (ECP) is seen as a low cost and effective deposition technique with promise. ECP is generally performed by introducing a substrate into a plating bath and applying a potential between an anode disposed in the bath and the substrate (e.g., a seed layer form on the substrate). The copper ions plate out of solution and deposit onto the substrate.
However, copper is difficult to pattern and etch. Accordingly, copper features are formed using damascene or dual damascene processes. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. The features typically have barrier materials deposited on their surfaces to form a conformal barrier layer. Copper is then deposited over the barrier layer and the surrounding field area. The copper deposited on the field is then removed by CMP to leave the copper filled feature. Both abrasive and abrasive-free CMP are currently available to remove copper.
To achieve complete planarization over wide features, it is necessary to deposit a copper thickness approximately 1.4-2.0 times that of the intra-level dielectric (ILD) thickness. For typical power lead levels, a 2.0 &mgr;m thick copper layer is required. However, the deposition of such a thick copper layer limits throughout of CMP processing.
One problem with CMP of copper is the tendency of copper surfaces to dish as a result of polishing. Dishing can result from copper over-polish used to clear all copper formed on the field across the wafer. One area where dishing may occur is in areas where conductive features exceed five microns. This is particularly problematic in some current designs where the conductive features are often greater than about fifty microns. To prevent excessive dishing in these areas during CMP processing, oxide pillars are typically interposed in these features to reduce the width of the conductive feature exposed to CMP processing. To reduce the cost of device fabrication, it would be advantageous to develop a deposition and planarizing apparatus and method that minimizes dishing and the need to use oxide pillars in large feature areas.
As a result, there is a need for an apparatus and method for depositing and polishing a metal layer, such as a copper layer, on a substrate.
SUMMARY OF THE INVENTION
The present invention generally provides an apparatus for depositing and polishing a material on a substrate. In one embodiment, the apparatus includes a basin, a cover, a permeable disc, an anode and a polishing head. The permeable disc is disposed in the basin between the cover and the basin's bottom. The cover has an aperture disposed therein that includes a plurality of pins. The pins extend radially into the aperture and are adapted to support the substrate. The anode is disposed in the basin between the disc and the bottom of the basin. The polishing head is adapted to retain the substrate during processing and includes a retaining ring. The retaining ring has a plurality of grooves disposed therein that mate with the pins when the polishing head is disposed in the aperture. When the substrate is electrically biased through the pins, the potential between the substrate and the anode causes material to be deposited on the substrate's surface.
In another embodiment, the apparatus additionally comprises one or more polishing stations disposed adjacent the cover.
REFERENCES:
patent: 4793895 (1988-12-01), Kaanta et al.
patent: 4934102 (1990-06-01), Leach et al.
patent: 5217586 (1993-06-01), Datta et al.
patent: 5225034 (1993-07-01), Yu et al.
patent: 5453312 (1995-09-01), Haas et al.
patent: 5534106 (1996-07-01), Cote et al.
patent: 5543032 (1996-08-01), Datta et al.
patent: 5567300 (1996-10-01), Datta et al.
patent: 5575706 (1996-11-01), Tsai et al.
patent: 5692950 (1997-12-01), Rutherford et al.
patent: 5738574 (1998-04-01), Tolles et al.
patent: 5804507 (1998-09-01), Perlov et al.
patent: 5807165 (1998-09-01), Uzoh et al.
patent: 5846882 (1998-12-01), Birang
patent: 5911619 (1999-06-01), Uzoh et al.
patent: 6004880 (1999-12-01), Liu et al.
patent: 6024630 (2000-02-01), Shendon et al.
patent: 6066030 (2000-05-01), Uzoh
patent: 6090239 (2000-07-01), Liu et al.
patent: 6103096 (2000-08-01), Datta et al.
patent: 6132587 (2000-10-01), Jorne et al.
patent: 6136163 (2000-10-01), Cheung et al.
patent: 6217734 (2001-04-01), Uzoh
patent: 6228231 (2001-05-01), Uzoh
patent: 6234870 (2001-05-01), Uzoh et al.
patent: 6261433 (2001-07-01), Landau
patent: 2001/0024878 (2001-09-01), Nakamura
patent: 98/49723 (1998-11-01), None
patent: 00/26443 (2000-05-01), None
patent: 00/59008 (2000-10-01), None
patent: 00/59682 (2000-10-01), None
Dordi et al. “Electro-Chemical Deposition System” U.S. patent application Ser. No.: 09/289,074, filed Apr. 8, 1999.
Ettinger et al. “Metho
Li Shijian
Sun Lizhong
Tsai Stan D.
Applied Materials Inc.
Moser Patterson & Sheridan
Valentine Donald R.
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