Memory array organization

Details Memory array organization Memory array organization

2001-01-03

2003-07-22

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S767000, C714S769000, C714S774000

Reexamination Certificate

active

06598199

ABSTRACT:

BACKGROUND
1. Field
This invention relates generally to memory arrays. In particular, the present invention relates to the organization of a memory array with error correction.
2. Description
Server devices in a network typically have more stringent memory processing characteristics than desktop personal computers. In particular, it is desireable that servers reliably store a great deal of information and quickly distribute that information in response to requests from other devices in the network. There are numerous transactions, such as for bank accounts, etc., in which it is desireable that the data be correctly stored and that an error be covered or corrected as software is running. For example, if the data is a credit card account number, corruption of the data could result in the wrong account being charged, etc. Consequently, server devices should be able to either: correct erroneous data stored in its memory and continue processing or, if the data cannot be corrected, stop the transaction and provide an error notice.
Corruption sometimes occurs in the storage medium of the memory itself. Therefore, servers typically have error correction capability support for the stored data in the memory interface. This error correction may include, for example, Single Bit Correct/Double Bit Detect (“SBCDBD”) and Double Bit Correct/Triple Bit Detect (“DBCTBD”). Some server memory arrays also have a “chip kill” feature—the ability to detect the complete or substantial failure of a single memory device in the array.
Some dynamic random access memory (“DRAM”) arrays in servers are specifically designed to use error correction codes (“ECC”), which are additional memory bits stored along with the data, to detect and correct errors of the data stored in the memory. Full error correction codes employ at least one or two extra bits for each 8-bit byte of data. ECC memories in server devices storing 16-bit data frequently have 3 additional bits used for error correction.
Some memory arrays specifically designed for these servers use 72 bit data words (to provide eight additional bits for error correction) instead of the 64 bit data path width of the standard memory and memory interface used in desktop systems without any error detection circuitry. But such specialized memory arrays are less available and higher in cost than the standard desktop memory.
Furthermore, some memory devices such as RDRAM™ brand dynamic random access memory (available from Rambus, Inc., of Mountain View, Calif.) transfer data over a narrow data path having less bits than the data words transferred into and out of the processor. These narrow data path memory devices are more expensive and do not easily accomodate the full error correction desired in some environments such as in servers. Consequently, it is desireable to devise a manner of organizing such narrow data path memory devices to accomodate full error correction.
SUMMARY
The present invention is directed to a method of organizing memory devices into a memory array having error correction. In a first aspect, a memory array has Rambus Direct Random Access Memories (RDRAM™s) coupled to respective first RDRAM™ channels, at least one of which stores and transfers a respective mutually exclusive group of the bits of a data word over its respective first RDRAM™ channel in parallel with the other first RDRAM™s. There is also a second RDRAM™ coupled to a respective second RDRAM™ channel, the second RDRAM™ storing and transferring error correction data used in detecting and correcting errors in the data stored in the first RDRAM™s.


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