Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-12-13
2003-09-16
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000
Reexamination Certificate
active
06622270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of testing a semiconductor memory chip and more specifically to optimizing repair time using a fuse identifier associated with the semiconductor memory chip.
2. Discussion of the Related Art
In order to ensure that a semiconductor device, such as a DRAM, is reliable, multiple tests are performed on the device before and after packaging.
A DRAM includes an array of memory cells or bits in rows and columns. After packaging, a plurality of tests are performed on the device in order to determine whether there is a defect in the array of bits that will fail over time. For example, burn-in testing is performed to accelerate failure using voltage and temperature stress. When a failed memory cell is detected, the row or column in which the failed memory cell is located is substituted by a redundant row or column, respectively. After packaging, this substitution is performed using antifuses in the memory chip.
Antifuses are capacitors including two conductive layers spaced by a thin insulative material, such as silicon nitride. Under normal biasing conditions, no DC current flows through the antifuse. Upon application of an excessive bias across the two conductive layers, however, the thin insulative material breaks down, thereby shorting the two conductive layers. Thus, redundant memory elements coupled to the antifuses can be selectively connected to circuiting external to the memory array by applying the excessive bias to desired antifuses.
If a memory chip fails any one of the tests, it is placed in a failure bin and becomes a candidate for antifuse repair. During the repair step, redundancy analysis is performed on each of the failed memory chips which involves repeating tests in order to identify specific bits that have failed. Once a failed bit is located, either the entire row or column in which it is located is replaced with a corresponding redundant row or column. Redundancy analysis has half the throughput of the initial testing analysis because the initial analysis typically tests 64 sites wide on a chip such as 16M DRAM while redundancy analysis only tests 32 sites wide on the memory chip.
Due to the relatively large amount of time required to perform redundancy analysis, only a subset of tests are run, such as the ten most commonly failed tests. However, faulty memory cells in chips failing tests not among these top ten failing tests will not be detected and repaired during redundancy analysis.
SUMMARY OF THE INVENTION
In accordance with the purpose of the invention, as embodied and broadly described herein, a method is provided for testing integrated circuits or semiconductor memory chips, such as DRAMs, having a plurality of bits or memory cells. Each memory chip has a unique identifier, preferably a fuse identifier having a series of selectively blown fuses corresponding to a unique binary number, located on the memory chip. The information contained in the fuse identifier is also stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and the failed test identifier is stored in the database with the associated memory chip identifier. In order to repair the memory chip, failed test data are read out of the database and only selected tests which the chips failed are again performed on the failed memory chip in order to determine which bit in the memory chip is faulty. The failed bits are then repaired preferably by substitution of redundant rows or columns.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Ton David
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