Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-29
2003-05-06
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S697000
Reexamination Certificate
active
06559009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a high-coupling ratio flash memory array, and more particularly, to a method of planarizing a flash memory to prevent CMP dishing, to increase cell uniformity and to increase the coupling ratio between the floating gate and the control gate.
2. Background of the Invention
In a flash memory cell, an initial memory array and a peripheral region are first defined on a silicon substrate. The initial memory array typically includes columns of polysilicon lines (also referred to as Poly-1 lines) and a plurality of gaps formed therein between two adjacent Poly-1 lines. The Poly-1 lines of the memory array function as a bottom portion of a floating gate of the flash memory. A high-density plasma chemical vapor deposition (HDPCVD) process is normally performed to deposit an HDP oxide layer over the memory array and partially filling the gaps. In most cases, each Poly-1 line comprises an additional nitride cap layer formed on its surface. A chemical mechanical polishing process (CMP) is thereafter used to achieve cell planarization for facilitation of subsequent processes using the nitride cap layer as a polishing stop layer.
In manufacture of the flash memory, uniformity of thickness of the HDP oxide layer at the bottom of each gap between two adjacent Poly-1 lines (hereinafter referred to as bottom thickness) is of primary concern for flash memory cell performance. In regards to the deposition variation of the bottom thickness of the HDP oxide layer, the typical uniformity variation at one sigma statistical standard deviation of error is approximately 2% (±1&sgr;) . The use of the CMP process exacerbates the decrease in uniformity as device packing density increases, and is likely due to the well-known dishing effects. Typically, the uniformity variation at one sigma statistical standard deviation resulting from the use of the CMP process is approximately 3-4% (±1&sgr;), to thereby produce an undesirable total variation of about 4% (±1&sgr;).
Please refer to
FIG. 1
to
FIG. 7
of the cross-sectional diagrams of fabricating a flash memory cell on a semiconductor wafer
10
according to the prior art. As shown in
FIG. 1
, a gate oxide layer
14
is first formed on a silicon substrate
12
of a semiconductor wafer
10
. Next, a polysilicon layer
16
, and a silicon nitride cap layer
18
are formed, respectively, on the gate oxide layer
14
. As shown in
FIG. 2
, a lithographic process is then used to pattern a photoresist layer
20
for defining a peripheral region
15
and a memory array area
17
. As shown in
FIG. 3
, using the photoresist layer
20
as a hard mask the silicon nitride cap layer
18
and the polysilicon layer
16
are etched to form columns of capped Poly-1 lines
21
. As well, a wide gap
22
is produced between the peripheral region
15
and the memory array area
17
, and a plurality of gaps
23
are formed in the memory array area
17
between two adjacent Poly-1 lines
21
. The photoresist layer
20
is then removed.
As shown in
FIG. 4
, after the removal of the photoresist layer
20
, a high-density plasma chemical vapor deposition (HDPCVD) process is then performed to deposit an HDP oxide layer
24
on the surface of the semiconductor wafer
10
and filling in both the gap
22
and the gaps
23
. As shown in
FIG. 5
, a chemical mechanical polishing (CMP) process is then performed to remove the portion of the HDP oxide layer
24
atop the Poly-1 lines
21
and achieve cell planarization. As shown in
FIG. 6
, a wet etching process, such as hot phosphoric acid etching, is used to completely remove the silicon nitride layer
18
to expose the underlying polysilicon layer
16
. ACVD process is then performed to deposit a polysilicon layer
26
, followed by the deposition of a photoresist layer
28
and then its patterning by a conventional lithographic process.
As shown in
FIG. 7
, the photoresist layer
28
is used as a hard mask to etch the polysilicon layer
26
down to the surface of the HDP oxide layer
24
to form a floating gate
29
. The floating gate
29
is formed of both the polysilicon layers
26
,
16
. After the removal of the photoresist layer
28
, a thin oxide-silicon-oxide (ONO) dielectric layer
32
is formed on the surface of the semiconductor wafer
10
and covering both the HDP oxide layer
24
and the floating gate
29
. Finally, a doped polysilicon layer
34
is formed over the ONO dielectric layer
32
to form the control gate.
In the prior art, the dishing effects that occur in the CMP process greatly affect the uniformity of the bottom thickness of the HDP oxide layer
24
. The occurrence of dishing can also lead to erosion of the exposed Poly-1 line
21
near the wide gap
22
. As a result, both dishing and a decrease in uniformity of the bottom thickness affect the electrical performance and reliability of the flash memory cell.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of cell planarization to prevent dishing, increase the uniformity of HDP thickness as well as to increase the coupling ratio of the floating and control gate to effectively enhance the performance of the flash memory cell.
In the present invention, a gate oxide layer is first formed on a silicon substrate of a semiconductor wafer. Then, a first polysilicon layer, and a silicon nitride cap layer are deposited, respectively, on the gate oxide layer. A lithographic process is then used to pattern a first photoresist layer and define a memory array area and a peripheral region. The first photoresist layer is then used as a hard mask to etch the silicon nitride cap layer and the first polysilicon layer to form columns of silicon-capped poly lines. Also, a wide gap is formed at the boundary between the memory array area and the peripheral region, and a plurality of gaps are formed in the memory array area. Following removal of the first photoresist layer, an HDP oxide layer is then deposited over the surface of the semiconductor wafer via an HDP deposition process. Next, a photoresist (PR) is coated over the HDP oxide layer and filling the gaps to achieve cell planarization. Thereafter, an oxide etch back process is performed to remove a portion of the PR coating. A stripping process is then used to strip both the PR coating and the silicon nitride layer to expose both the surface of the first polysilicon layer and that of the HDP oxide layer.
The method of the present invention replaces the prior art use of chemical mechanical polishing with the coating of a photoresist in order to achieve cell planarization. As a result, dishing is prevented and the standard deviation of error occurring from the use of the CMP process is removed to increase the electrical performance of the flash memory cell. Also, following cell planarization and stripping of both the PR coating and the silicon nitride layer, the ends of the HDP oxide layer block allow for a greater contact surface between the floating gate and the control gate. As a result, the coupling ratio between the gates increases to thereby improve the read/write speed of the flash memory.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5015602 (1991-05-01), Van Der Plas et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5962889 (1999-10-01), Yamauchi et al.
Wolf S. “Silicon Processing for the VLSI-ERA: vol. 2-Process Integration”, 1990, Lattice Pr., vol. 2, pp. 222-223.
Foong Suk-San
Fourson George
Macronix International Co. Ltd.
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