Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-27
2003-07-15
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S285000, C257S347000
Reexamination Certificate
active
06593192
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to methods of fabricating dual-gate transistors and more specifically to methods of fabricating such transistors with self-aligned gate structures on semiconductor on insulator substrates.
BACKGROUND
Increased performance, both with regard to more complex functionality and higher speeds, is generally the goal of efforts in advancing the semiconductor arts. One method that has been used for achieving this goal is scaling downward the size of transistors used in advanced semiconductor devices. However, as devices have become smaller, such scaling has become problematic due to short channel effects, insufficient drive voltages and inadequate sub-threshold performance. Thus to continue to increase or enhance device performance, particularly transistor device structures, it would be desirable to create transistor device structures that overcome or reduce the above mentioned problems.
One such transistor structure that theoretically offers advantages that overcome the aforementioned problems of scaling device size downward is the dual-gated transistor structure. However, such transistors have proven difficult to fabricate, making it difficult to take advantage of increased drive current and sub-threshold performance. This difficulty is the result of the absence of a technique or method for accurately aligning the front and back gate structures to one another. As a result of this deficiency, alternate transistor structures that do not offer all of the advantages of dual-gate transistors have been pursued. Exemplary of such alternate structures are “surround gate” and “DELTA” gate transistors. However, while such alternate devices provide some of the benefit predicted for dual-gated transistors, these partial benefits are only realized at the expense of difficult manufacturing processes that result in an integrated circuit having highly irregular surface topology due to the vertical nature of such alternate devices.
It would therefore be advantageous to have methods for forming dual-gated transistor devices that employ straightforward semiconductor fabrication methods. It would also be advantageous if such methods would be useful to form dual-gated transistors that have an essentially standard transistor surface profile, thus avoiding the problematic highly irregular surface topology of the aforementioned alternate devices. In addition, it would be advantageous if such methods could be employed to form such dual-gated transistor devices having high drive current and superior sub-threshold performance.
SUMMARY
Embodiments in accordance with the present invention provide methods of fabricating dual-gated transistor structures. Thus, a first transistor gate is formed adjacent a first side of the semiconductor layer of a semiconductor-on-insulator (SOI) substrate and source/drain (S/D) contact structures are formed proximate laterally opposing sides of the first transistor gate structure. These S/D structures are formed such that they extend into the insulator layer, adjacent a second side of the semiconductor layer opposing the first side, of the SOI substrate. Subsequently, material of the insulator layer is removed from between the S/D contact structures. After the removing, second transistor gate structures are formed adjacent the second side, between the S/D contact structures.
Generally, embodiments in accordance with the present invention provide that the S/D contact structures are operatively coupled to both the first and second gates as well as to S/D regions formed in the semiconductor layer. Such embodiments also provide that the first and the second transistor gates are formed on opposing sides of a semiconductor layer in such a manner that the gates are self-aligned to one another to define, and provide for control of, a common channel region.
In some embodiments of the present invention, the S/D contact structures are spaced from the first gate structure by spacer structures formed from an insulating material. Thus the spacer structures serve to define the position of such the source/drain contact structures laterally, with respect to the gate structures, a first portion of the S/D contact structures being adjacent the spacers.
In embodiments in accordance with the present invention, the S/D contact structures of the first transistor are formed to extend into the insulating layer of the SOI substrate. In some embodiments, such S/D structures extend through the insulating layer and into the bulk semiconductor substrate.
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Dennison Charles H.
Keeth Brent
Zahurak John K.
Chaudhuri Olik
Kebede Brook
Micro)n Technology, Inc.
Wells St. John P.S.
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