Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-02-12
2003-09-16
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S694000, C438S710000
Reexamination Certificate
active
06620733
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacture. More particularly, the present invention relates to the elimination of micromasking during etching of low-k dielectrics during the processing of semiconductor wafers.
BACKGROUND OF THE INVENTION
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO
2
, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO
2
, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO
2
may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO
2
, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. Many of these new dielectrics are organic compounds. In the specification and claims, a low-k material is defined as a material with a dielectric constant “k” that is less than 4.
Low-k materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare™ manufactured by Allied Signal® of Morristown, N.J., a division of Honeywell, Inc., Minneapolis, Minn.; one or more of the Parylene dimers available from Union Carbide® Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK®. One PTFE suitable for IC dielectric application is SPEEDFILM™, available from W. L. Gore & Associates, Inc, Newark, Del. SiLK®, available from the Dow® Chemical Company, Midland, Mich., is a silicon-free BCB.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer. Low-K organic polymers in general can be etched by oxidation (e.g. oxygen-based) or reduction (e.g. hydrogen-based) chemical processes.
The etching of dielectrics may be advantageously accomplished in a dual-frequency capacitively-coupled, (DFC) dielectric etch system. One such is Lam® Research model 4520XL
E
™ and Exelan-HP™, available from Lam® Research Corporation, Fremont Calif. The 4520XL
E
™ system processes an extremely comprehensive dielectric etch portfolio in one system. Processes include contacts and vias, bilevel contacts, borderless contacts, nitride and oxide spacers, and passivation.
Advanced etch systems like the 4520XL
E
™ perform several processes in the same system. By performing many different semiconductor fabrication steps in a single system, wafer throughput can be increased. Even further advanced systems contemplate the performance of additional steps within the same equipment. Again by way of example, but not limitation, Lam™ Research Corporation's Exelan™ system is a dry etch system capable of performing many process steps in a single apparatus. Exelan™ enables hardmask open, inorganic and organic ARC etch, and photoresist strip to be performed in situ with a single chamber. This system's extensive process portfolio includes all dual damascene structures, contacts, vias, spacers, and passivation etch in doped and undoped oxides and low-k dielectrics required in the sub-0.18 micron environment. Of course, the principles enumerated herein may be implemented in wide variety of semiconductor fabrication systems, and these principles specifically contemplate all such alternatives.
As used herein, the term in situ refers to one or more processes performed on a given substrate, such as a silicon wafer, in the same piece of semiconductor fabrication equipment without removing the substrate from the equipment.
Many current integrated circuit fabrication technologies utilize a photoresist stripping step following one or more of the patterning steps used to form the features in the wafer. Because many photoresists have similar chemical compositions with respect to low-k dielectrics, especially organic low-k dielectrics, such as SiLK, in order to ensure good dimensional control during the etching of a feature in a wafer, a hard mask is often employed beneath the photoresist.
An example wafer stack incorporating a hard mask layer is shown at FIG.
1
A. The wafer,
1
, having a patterned layer of photoresist,
10
, is shown. In this example, wafer
1
includes a silicon substrate,
22
having deposited thereon a silicon carbide or silicon nitride barrier layer,
20
. Deposited over barrier layer
20
is a first layer
18
of organosilicate dielectric, for instance Novellus Coral™. A metalized structure, not shown, may be formed under the first layer of organosilicate dielectric. A thin silicon carbide trench stop layer
16
is disposed between first blank layer
18
to form a dual damascene structure, not shown. A second blank layer,
14
, also of Coral™ is deposited over trench stop layer
16
. A hard mask layer
12
is deposited over second organosilicate layer
14
, completing the example in wafer stack. Hard mask may be formed of SiO2, Si3N4, or other hard mask materials, especially inorganic hard mask materials. Patterned photoresist layer
10
, previously discussed, is applied over hard mask
12
. Of course, it will be recognized by those having skill in the art that this wafer stack is exemplary only. Alternative structures and films, known to those having skill in the art may be utilized to implement alternative integrated circuit designs.
Having reference now to
FIG. 1B
, as etching proceeds, especially the etching of low-K OSG dielectric layers
14
and
18
, as shown in
FIG. 1B
, photoresist layer
10
is etched away, exposing portions of hard mask layer
12
, beneath. As etching continues, ion bombardment of the hard mask layer also sputters away a portion of hard mask layer
12
. Some of the sputtered hard mask material is re-deposited on surface of the wafer and throughout the reaction chamber. Section “A” is enlarged at FIG.
1
C. At least some of this sputtered material is further deposited at the bottom of etched features during etching, as shown at
36
, in FIG.
1
C. The amount of micromasking increases with increased ion density and ion energy. Micromasking is more evident in large feature sizes
Beyer Weaver & Thomas LLP
Lam Research Corporation
Vockrodt Jeff
Zarabian Amir
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