Method for forming dielectric stack without interfacial layer

Details Method for forming dielectric stack without interfacial layer Method for forming dielectric stack without interfacial layer

2001-02-05

2003-03-04

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S204000, C438S287000, C438S404000, C438S624000

Reexamination Certificate

active

06528374

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication of semiconductor devices, and more particularly, to a method of forming a silicate based dielectric on a silicon substrate and a semiconductor device formed thereby.
2. Description of the Related Art
In semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices, a silicon dioxide (SiO
2
) based gate dielectric is formed on a silicon substrate. With increased miniaturization of transistors in CMOS devices, there has been an impetus to replace SiO
2
as the gate dielectric with alternative material that has a higher dielectric constant. This is because the feasibility of CMOS scaling is increasingly dependent on the gate dielectric.
To increase the integration density of semiconductor devices, the thickness of SiO
2
layers has been reduced. However, the reduction of the thickness of SiO
2
layers causes a problem of diminishing reliability of the SiO
2
layers as gate dielectrics. Evidence of diminished reliability for SiO
2
layers thinner than 25 Å has been reported, and more recently revised to 16 Å. More recent assessments indicate diminished reliability for thickness below 16 Å.
Further reduction of the thickness of SiO
2
layers would eventually require replacement of the SiO
2
layers with some alternative material with a higher dielectric constant. An approach pursued by numerous groups is to create a dielectric stack, with an interfacial layer of SiO
2
and an overlayer of a high permittivity dielectric, such as a metal oxide or silicate. Although the interface between silicon substrate and SiO
2
layer is known to have good stability, this approach still has such drawbacks as the SiO
2
layer limits the capacitance of the stack and fabrication of the stack on an atomic length scale.
Thus, alternative dielectrics are highly desirable if they can provide an equivalent capacitance with a reduced leakage current, taking account of numerous other considerations such as compatibility with silicon, thermal robustness, and ease of integration and deposition. A practical limit on the capacitance of a metal-oxide or a silicate on silicon structure is posed by the occurrence of an interfacial layer of SiO
2
. The interfacial layer may arise from substrate oxidation during dielectric growth, or it may be caused by post-growth oxidation, or it could even be a remnant from a preexisting SiO
2
layer.
Fabrication of a semiconductor stack formed of metal-oxide and silicon layers adjacent to each other is severely hampered by the unfortunate fact that most metal-oxides are highly permeable to oxygen. If deposition of a metal-oxide layer is performed at elevated temperatures and in an oxygen rich ambient, excess oxygen can diffuse through the metal-oxide dielectric layer and react with the silicon substrate. For example, when a compound such as zirconium (Zr) oxide or hafnium (Hf) oxide is deposited on hydrofluoric (HF) etched silicon surfaces, there is generally formed an interfacial SiO
2
layer having the thickness of 5-15 Å. Metals such as lanthanum (La) and yttrium (Y), which easily form silicates, develop both an interfacial SiO
2
layer and a significant level of Si (e.g., 10-15 at %), which may further reduce the capacitance of the stack. Further, once the metal-oxide layer is deposited, post-growth oxidation may be needed to reduce the leakage current, which will also reduce the capacitance of the stack.
It is well known that when SiO
2
is heated in the ultrahigh vacuum (UHV), it is converted into SiO which is volatile. Thus, SiO
2
formed on a substrate can be removed from the substrate by thermal treatments in the UHV circumstances. Furthermore, the reaction is known to be inhomogeneous, starting with pinholes that gradually merge. The reaction takes place at temperatures ranging from 800° C. to 1050° C., depending on the thickness of the SiO
2
layer.
However, although most metal-oxides are highly permeable to oxygen, the removal of the SiO
2
layer formed on the Si substrate during a metal-oxide deposition has not been successful. For example, investigation of a film formed of layers of “ZrO
2
/SiO
2
/Si(001)” shows that at temperatures between 900° C. and 1000° C., the film is converted into islands of Zr silicide. Another investigation of a film where Al
2
O
3
layer is deposited on a Si substrate shows a different pathway to dissociation, that is, volatilization of the metal and conversion of the surface to atomically clean, albeit rough, Si(100). In other investigations as well as the above examples, it is shown that oxygen loss is accompanied by the catastrophic destruction of the dielectric.
In addition to the above-mentioned approaches to solve the SiO
2
layer problem, there has been provided a method of minimizing Si-intermixing between a metal oxide layer and a Si substrate. This method is described in “Yttrium Silicate Formation on Silicon: Effect of Silicon Pre-oxidation and Nitridation on Interface Reaction Kinetics”, by Chambers et al., October 2000, Applied Physics Letters, Vol. 77, No. 15, pp. 2385-2387. Chambers et al. describe a method for minimizing Si-intermixing by introducing barrier layers of nitrided silicon interfacial layer between a metal-oxide layer and a Si substrate. However, Chambers et al. have not provided any information regarding the removal of SiO
2
formed by depositing the metal-oxide on the Si substrate.
Therefore, a need exists for a method of forming a dielectric stack having a dielectric layer which replaces a conventional SiO
2
-based dielectric layer. Further, it will be advantageous to provide a method of forming a dielectric stack which has characteristics of increased capacitance and reduced leakage current.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of forming a dielectric stack having substantially no interfacial layer between a silicon substrate and a dielectric layer.
It is another object of the present invention to provide a method of forming a dielectric stack having a thin silicate layer as a dielectric layer formed directly on a silicon substrate.
It is further object of the present invention to provide a method of forming a dielectric stack having increased capacitance and reduced leakage current.
It is still another object of the present invention to provide a method of forming a dielectric stack having a silicate layer and a silicon substrate without performing an HF etching of the silicon substrate.
To achieve the above and other objects, the present invention provides a method of forming a dielectric stack device having a plurality of layers, comprising the steps of providing a silicon substrate; forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate; and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at temperatures between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes.
The formation of the metal-oxide layer may include forming the silicon oxide layer on the silicon substrate, and depositing the metal-oxide layer on the silicon oxide layer. Alternatively, the formation of the metal-oxide layer may include depositing the metal-oxide layer on the silicon substrate, wherein the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The silicon oxide layer may be a silicon dioxide layer or a silicon oxynitride layer. The metal-oxide layer preferably comprises Yttrium. The annealing is performed at temperatures which are directly related to thickness of the metal-oxide layer and/or the silicon oxide layer. For example, in case that the metal-oxide or silicon oxide layer is thicker, the temperatures for the annealing need to be higher.
The present invention also provides a dielectric stack device comprising a silicon subst

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