Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-23
2003-07-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S637000, C438S643000, C438S653000, C438S672000, C438S688000
Reexamination Certificate
active
06589863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layered interconnection structure in which interconnections and plugs are provided in the form of damascene and a manufacturing method thereof.
2. Description of the Related Art
In recent years, as the LSI (Large Scale Integrated Circuit) achieves a still more densely spaced arrangement, techniques to form a multi-layered interconnection with a three-dimensional interconnection structure have been acquiring further importance. In the process flow of manufacturing a multi-layered interconnection, every step of depositing and working a metal, depositing an insulating film and applying planarization thereto, and forming a through hole and damascening by inlaying a metal therein must be performed at a temperature below the heat-proof temperature of each metal material. Moreover, the actual process must be designed to have simple and practical steps, while paying, at the same time, due regard to the yield and reliability of the final product thereby.
Meanwhile, in order to satisfy demands that the element should have a still higher speed, low-resistance materials such as copper have become in wide use. With copper, however, patterning by means of etching is difficult to perform. Therefore, when copper is used, an interconnection must be formed by a method different from the conventional method used for forming an Al interconnection.
Under such circumstances, extensive investigations are currently conducted over matters concerning a method of forming a damascene-type multi-layered interconnection that meets specific requirements of a new interconnection material such as copper.
Now, referring to
FIGS. 8
to
12
, a conventional method of forming a copper damascene interconnection structure is described herein below.
First, a lower layer interconnection is formed as follows.
After a metal film
1
is formed on a semiconductor substrate (not shown in the drawings), a plasma SiO
2
film
2
(100 nm in thickness), a HSQ (Hydrogen Silisesquioxane) film
3
(400 nm in thickness), a plasma SiO
2
film
4
(100 nm in thickness), a HSQ film
5
(400 nm in thickness) and a plasma SiO
2
film
6
(200 nm in thickness) are formed thereon in this order (FIG.
8
(
a
)). A photoresist
7
patterned into a prescribed shape is then formed over that (FIG.
8
(
b
)). Using this photoresist
7
as a mask, dry etching is applied thereto so as to form a trench that reaches the metal film
1
(FIG.
8
(
c
)). After that, a strip treatment of the photoresist
7
is carried out by means of ashing with the oxygen plasma and cleaning with a stripper containing amines. Next, a photoresist
7
′ having a wider opening than the width of this trench is formed (FIG.
8
(
d
)), and another dry etching is applied thereto, using this photoresist
7
′ as a mask, and thereby a sectionally partially T-shaped trench is formed (FIG.
9
(
a
)).
After removing the photoresist
7
′ (FIG.
9
(
b
)), a barrier metal film
8
(50 nm in thickness) made of TiN is deposited over the entire surface by the sputtering method (FIG.
9
(
c
)). Further, over that, a seed film (not shown in the drawings) for the purpose of performing electroplating with copper is deposited to a thickness of 100 nm by the sputtering method, and thereon a copper film
10
(1000 nm in thickness) is grown by electroplating so as to fill up the trench section (FIG.
9
(
d
)). Subsequently, portions of the copper film
10
as well as the barrier metal film
8
which are formed in a region other than the trench section are removed by the CMP (Chemical Mechanical Polishing) and thereby a lower layer interconnection is accomplished (FIG.
10
(
a
)).
Over this lower layer interconnection, a SiN film
20
is formed by the plasma CVD (Chemical Vapour Deposition) method (FIG.
10
(
b
)). This SiN film
20
serves as an etching stopper when a through hole between the lower layer and the upper layer interconnections is formed as described below. With the SiN film
20
being set, degradation of the lower layer interconnection at the time of formation of the through hole can be suppressed to a certain degree. Further, the SiN film can prevent metal particles of copper and the like from diffusing into an interlayer insulating film and giving adverse effects on the element. The film thickness of the SiN film
20
is normally 50 nm or so.
Next, an upper layer interconnection is formed in the similar way as the formation of the lower layer interconnection. A HSQ film
13
(400 nm in thickness), a plasma SiO
2
film
14
(100 nm in thickness), a HSQ film
15
(400 nm in thickness) and a plasma SiO
2
film
16
(200 nm in thickness) are formed in this order. A photoresist
17
patterned into a prescribed shape is then formed over that (FIG.
11
(
a
)).
Using this photoresist
17
as a mask, dry etching is applied thereto. At this, owing to a difference in etching rate between the HSQ film
13
and the SiN film
20
, the etching is stopped at the top section of the SiN film
20
(FIG.
11
(
a
)). Following this, together with strip of the photoresist
17
, the deposit produced by etching is removed, by means of ashing with the oxygen plasma and cleaning with a stripper. After that, a photoresist
17
′ having a wider opening than the width of this trench is formed, and another dry etching is performed, using this photoresist
17
′ as a mask, and thereby a sectionally partially T-shaped trench is formed (FIG.
11
(
b
)). Next, the photoresist
17
′ as well as the etching deposit produced by etching are removed by means of oxygen plasma ashing and cleaning with a stripper. Next, the SiN film
20
is etched by dry etching, which exposes the copper film
10
(FIG.
11
(
c
)). After that, cleaning with a stripper is again applied thereto and the etching deposit produced by this dry etching or the deposit of SiN origin is removed.
A barrier metal film
18
(50 nm in thickness) and a copper film
19
(1000 nm in thickness) are formed in this order so as to fill up completely the trench section which is formed as described above, and thereby the trench section is damascened. Subsequently, carrying out the planarization by the CMP, the multi-layered interconnection structure as shown in
FIG. 12
is formed.
In the conventional technique describe above, a SiN film is formed over the lower layer interconnection with the object of providing an etching stopper film as well as suppressing diffusion of copper or the like. However, considering the following adverse points given by this film, further improvements yet remain to be made.
Firstly, the parasitic capacitance between interconnections on the same interconnection layer becomes considerably large owing to the fringe effect.
FIG. 14
is a diagram to explain this phenomenon. Between the adjacent interconnections
50
and
51
at the same interconnection layer, there are present s parasitic capacitor
52
in which a SiO
2
film
54
serves as a dielectric film and a parasitic capacitor
53
in which a SiN film
55
serves as a dielectric film. Since the permittivity of the SiO
2
film is comparatively low, the effect of the parasitic capacitor
52
is relatively small. The permittivity of SiN is, however, approximately twice as much as that of SiO
2
so that the parasitic capacitor
53
has a large capacitance. In short, the presence of this parasitic capacitor
53
makes a cross talk between the interconnections
50
and
51
liable to happen.
Secondly, there are known to be problems such as degradation of the lower layer interconnection and contamination of the through hole which are apt to take place in the step of removing the SiN film. For the SiN film is an insulating film, the SiN film within the through hole must be removed. The removal of the SiN film is carried out by means of dry etching and, on that occasion, the deposit of SiN origin produced by this etching should be cleared off as well. Although the removal of the deposit of SiN origin can be normally made using a stripper for resist, this tends
Dickstein Shapiro Morin & Oshinksky LLP
Luu Chuong A.
NEC Electronics Corp.
Smith Matthew
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