Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-12-17
2003-09-23
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S161000
Reexamination Certificate
active
06624010
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 2001-384956, filed Dec. 18, 2001, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device, specifically to a method of manufacturing a semiconductor device having a thin film SOI structure in which imperceptible contact holes are formed.
2. Description of the Related Art
With an increase in the level of a high performance, an SOI-type semiconductor device is generally used in order to satisfying the requirement, instead of a semiconductor device having a bulk silicon substrate. The SOI-type semiconductor device includes an SOI substrate, which consists of a support substrate, a buried silicon oxide layer (BOX layer) and a silicon layer (SOI layer) formed on the BOX layer, and field effect transistors (FETs) are formed in the silicon layer. Thus, this type of the semiconductor device is called SOI (Silicon On Insulator) type semiconductor device.
According to the SOI-type semiconductor device, since the FETs are formed in a thin SOI layer formed on a BOX layer, a junction capacitance can be reduced, comparing to the semiconductor device having the bulk silicon substrate. As a result, high speed performance can be expected in such a SOI-type semiconductor device. Further, it is easy to isolate electrically each FET because the FETs are formed on the thin SOI layer. Specifically, the FETs are formed on the thin SOI layer, these FETs become fully depleted FETs. Thus, each fully depleted FET has small parasitic capacitance so that sub-threshold swing in the SOI-type semiconductor device becomes smaller than that in the semiconductor device having the bulk silicon substrate. As a result, the SOI-type semiconductor device draws attention as a low power consumption device. Moreover, since the width of the depletion region of each FET at its channel is determined by the thickness of the thin SOI layer, it is possible to control the short channel effect.
To perform the fully depleted operation of the SOI-type semiconductor device, it is required that the thickness of the SOI layer be reduced, with the progress of development of imperceptible device. For example, as shown in a thesis “Deep Sub-0.1 &mgr;m MOSFET's with very thin SOI layer for ultra-low power consumption”, C-II vol. J81-C-II No. 3, pp 313-319 published in 1998 by The Institute of Electronics, Information and Communication Engineers, the shorter the gate length is, like 0.35 &mgr;m, 0.25 &mgr;m, and 0.18 &mgr;m, the thinner the thickness of the SOI layer is, like 60 nm, 50 nm, and 40 nm. In the generation that the gate length is 0.1 &mgr;m, it is required that the thickness of the SOI layer be less than 20 nm.
When the thickness of the SOI layer becomes thinner, an operation ability using current may be decreased because the parasitic resistance at diffusion layers such as source and drain layers, increases. To avoid this issue, a silicide layer, such as a TiSi
x
layer or a CoSi
x
layer, is formed on the source and drain, whereby it is possible to reduce the resistance value. If the CoSi
x
layer is selected, three possible formations can be considered: one is Co
2
Si, another is CoSi, and the other is CoSi
2
. Since CoSi
2
has the lowest resistance value among them, the CoSi
2
layer may be selected and is selectively formed on the SOI substrate by the following process.
First, a Co layer is formed on the thin SOI layer. Then, a first anneal treatment is performed in the atmosphere of 550° C. for 30 seconds, and a second anneal treatment is performed in the atmosphere of 700° C. for 60 seconds successively. By performing the first and the second anneal treatments under the condition described above, the CoSi
2
layer can be formed consistently. The process of forming a CoSi
2
layer are reported in “Optimization of Series Resistance in Sub-0.2 mm SOI MOSFET's”, IEEE Electron device letters, Vol. 15, No. 09 Page 363 published in 1994.
However, the thinner the SOI layer is, the lesser the amount of silicon in the SOI layer to be consumed is. As a result, when the silicide layer is formed with using the thin SOI layer, it is difficult to control the composition in order to form the silicide layer consistently. Further, since the thickness of the SOI layer is reduced gradually by factors presented in each of the process steps before silicidation, it is further difficult to control the composition in order to form the silicide layer. As a result of this difficulty, a localized thin regions or defect spots of silicided SOI (void) may be formed during the CoSi
2
silicidation process at the second anneal treatment. Specifically, since it is generally found that the SOI layer is thinner in some areas (it is called “local thinning”), there is strong possibility that voids are preferentially formed in this areas during silicidation of the SOI layer. In the successive process for forming a contact hole in an insulating layer, which is formed on the silicide layer, when the contact holes are formed at the areas where the voids are formed, the contact holes reach the BOX layer underneath the silicide layer via voids. Since the BOX layer is formed of the same material (SiO2) of the insulating layer, the contact hole may reaches to the support substrate easily in case of the over-etching, resulting in the formation of threading pinholes through the BOX layer at the contact opening. In other words, the BOX layer can not stop etching for forming the contact hole because the insulating layer and the BOX layer are formed of the same material. As a result, a process yield (hereinafter referred as a BOX yield) is dramatically decreased.
SUMMARY OF THE INVENTION
An objective of the invention is to resolve the above-described problem and to provide a method of forming a semiconductor device, which avoid reaching a contact hole to a support substrate of a SOI substrate through a BOX layer.
The objective is achieved by a method of manufacturing a semiconductor device, including the steps of, (1) preparing an SOI substrate, (2) forming a metal layer on the SOI substrate, (3) performing a first anneal treatment to the metal layer at a relatively low temperature in order to transform the metal layer to a first silicide layer, (4) forming an insulating layer on the first silicide layer, and (5) forming a contact hole, which reaches the first silicide layer, in the insulating layer; and (6) performing a second anneal treatment to the silicide layer at a relatively high temperature in order to transform the first silicide layer to a second silicide layer.
REFERENCES:
patent: 6174806 (2001-01-01), Thakur et al.
patent: 6423599 (2002-07-01), Yu
“Deep Sub-0.1&mgr;m MOSFET's with very thin SOI layer for ultra-low power consumption”, C-II vol. J81-C-II No. 3, pp. 313-319 published in Mar., 1998 by The Institute of Electronics, Information and Communication Engineers Author: Makoto Takamiya, Yuri Yasuda and Toshiro Hiramoto Note: English Summary is attached.
“Optimization of Series Resistance in Sub-0.2 mm SOI MOSFET's”, IEEE Electron device letters, vol. 15, No. 09 p. 363 published in Sep., 1994 Author: Lisa T. Su, Melanie J. Sherony, Hang Hu, James E. Chung and Dimitri A. Antonidis.
Mimura Junichi
Oki Electric Industry Co. Ltd.
Potter Roy
LandOfFree
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