Method of forming dual-damascene interconnect structures...

Details Method of forming dual-damascene interconnect structures... Method of forming dual-damascene interconnect structures...

1998-09-09

2003-09-30

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S623000, C438S624000, C438S626000

Reexamination Certificate

active

06627539

ABSTRACT:

TECHNICAL FIELD
The present invention relates, generally, to methods and structures for multilevel interconnects in integrated circuits using planarization technology and, more particularly, to a dual-damascene approach employing a low-k dielectric.
BACKGROUND ART AND TECHNICAL PROBLEMS
Advanced semiconductor processing technology has permitted the fabrication of integrated circuit devices with sub-micron and sub-half-micron features sizes. This trend toward deep submicron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilayer interconnects. As a result, circuit performance in the deep submicron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors present on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well-controlled. Toward this end, recent trends emphasize the use of low resistance metals (e.g., copper) in conjunction with materials with low dielectric constants (“low-k dielectrics”) between metal lines.
Optical lithography techniques have, for the most part, managed to keep pace with deep sub-micron requirements through the use of off-axis illumination, phase shifting masks, and other methods known in the art. However, the decreasing depth of focus that accompanies this increase in resolution requires the production of highly planar surfaces during intermediary process steps. In light of the need for highly planar surfaces, traditional metal deposition and photolithographic techniques become progressively more ineffective as line widths are scaled and multiple layers of metal are used. For example, traditional metal deposition techniques can result in poor metal step coverage along the edges of the contact openings. Furthermore, wet chemical etch processes typically used with metals are difficult to control. While dry plasma etching may be employed with many metals, other metals with highly desirable properties (e.g., copper and gold) are generally not amenable to dry etching.
Modern semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) to create the interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 &mgr;m in width and on the order of 1.0 &mgr;m in height). In a paradigmatic CMP process, a resinous polishing pad (e.g., a polyurethane pad) is employed in conjunction with a mechanically and chemically active slurry. When pressure is applied between the polishing pad and the wafer being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack by the slurry. Thus, with the correct choice of slurry, pressure, and other process conditions, a highly planar surface may be formed on the wafer. For additional information regarding CMP process, see, for example, Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; and Arai, et al, U.S. Pat. No. 4, 805,348, issued February, 1989. The entire contents of these references are hereby incorporated by reference.
A fabrication method which employs CMP techniques and which addresses many of the above concerns is the so-called “damascene” process. Damascening acquired its name from an ornamental technique, generally attributed to metal-workers in ancient Damascus, which involved scribing or incising patterns into steel (most often swords) then filling the resulting grooves with gold or silver prior to final polish. Similarly, the modern semiconductor analog of this process involves, in the broadest sense, forming patterns in a dielectric layer, filling the resulting pattern with interconnect metal, then polishing away the excess metal on the wafer surface and leaving inlaid interconnect metal.
There are two major classes of damascene processes: single-damascene and dual-damascene. These two processes are illustrated in highly simplified form in
FIGS. 1A and 1B
(details of the various intermediary steps are discussed in further detail below). Briefly, and with reference to
FIG. 1A
, a single damascene process involves making contact to a lower conductor
102
(formed, for example, on substrate
107
) by patterning and forming a conductive plug
104
in one layer of dielectric
106
, then patterning second dielectric layer
110
, and forming the actual interconnect wiring metallization
108
in patterned dielectric layer
110
. In a dual-damascene process (FIG.
1
B), the interconnect wiring
108
and plug
104
are formed by patterning both the via and the trench patterns into dielectric
106
, then filling them simultaneously with metal. The dual damascene process offers the advantages of process simplification and low manufacturing cost.
Known methods of forming deep sub-half-micron damascene interconnect structures using low-k dielectrics are unsatisfactory in many respects. First, such methods typically employ a single-damascene approach. This results in a larger number of process steps—a number which tends to increase as feature size decreases—and, consequently, increases the overall product cost. In cases where a dual damascene architecture is employed, the low-k dual damascene processes typically require either a single damascene process as the starting point or CMP of the low-k material. In order to obtain the inlaid metal features with metal CMP, a damascene process requires a planar wafer surface. The first interconnect layers (e.g.., poly-Si conductor layer or lower levels of Al interconnects) on an IC chip are typically fabricated by a subtractive-etch process, and CMP of the subsequently deposited dielectric must be performed in order to obtain a planar wafer surface.
To avoid CMP of the low-k material—a process which is difficult to perform—known low-k dual damascene processes start from a previous level of conductors fabricated by a single damascene process. Before the single damascene conductors are fabricated, a planar wafer surface is obtained by CMP of a conventional dielectric, such as silicon dioxide, and the contact or via plugs are formed in the conventional dielectric layer. However, the single damascene step results in relatively high process cost, and the conventional dielectric between the single damascene conductor layer and the previous subtractive-etched conductor layer increases the capacitance and coupling between them.
Methods and structures are therefore needed in order to overcome these and other limitations in the prior art.
SUMMARY OF THE INVENTION
The above disadvantages of the prior art may be addressed by an improved dual-damascene process. Methods according to various aspects of the present invention provide techniques for fabricating IC interconnects using a dual-damascene process which incorporates a low-k dielectric material. In accordance with one aspect of the present invention, a low-k dual-damascene structure can be implemented without the necessity of using a previous single damascene wiring layer, and without CMP of the low-k dielectric. This structure simplifies the process, and effectively reduces intra-level and inter-level capacitance, reduces resistivity, and reduces noise related to substrate coupling. In accordance with a further aspect of the present invention, a modified silicon oxide material (e.g. silsesquioxane) is used for the low-k dielectric in conjunction with the silicon dioxide cap layers, allowing an improved process window and simplifying the etching process.


REFERENCES:
patent: 47896

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