Semiconductor devices and methods of manufacturing the same

Details Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same

2000-01-27

2003-03-11

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S297000, C438S298000, C438S301000, C438S306000, C438S225000, C438S224000, C438S227000, C438S294000, C257S327000, C257S336000, C257S337000, C257S338000, C257S339000

Reexamination Certificate

active

06531356

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices, and methods for their manufacture, including field effect transistors having a high breakdown voltage, and methods of manufacturing such semiconductor devices.
BACKGROUND
With recent downsizing and higher integration of semiconductor integrated circuits, there are demands for not only further downsizing of transistors, but also a higher density of integration in terms of well areas. Those demands also arise in a semiconductor device including a high-voltage endurable transistor to which a voltage not lower than 10 V, for example, is applied.
SUMMARY
One embodiment of the present invention relates to a semiconductor device including a first well formed in a semiconductor substrate and having a first conductivity type, a second well formed in the semiconductor substrate adjacent to the first well and having a second conductivity type, and a third well formed in the second well and having the first conductivity type. The device also includes a field effect transistor formed in each of said wells, the field effect transistor having an offset area in the semiconductor substrate around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under a LOCOS layer on the semiconductor substrate.
Another embodiment relates to a method of manufacturing a semiconductor device, including selectively forming, on a semiconductor substrate, an oxidation-resistant layer having a masking action against oxidation. An impurity of second conductivity type is introduced to the semiconductor substrate with the oxidation-resistant layer used as a mask, thereby forming a second well in the semiconductor substrate. A surface area of said second well is selectively oxidated with the oxidation-resistant layer used as a mask, thereby forming a LOCOS layer in the second well. The oxidation-resistant layer is removed and an impurity of the first conductivity type is introduced to the semiconductor substrate with the LOCOS layer used as a mask, thereby forming a first well in the semiconductor substrate in adjacent relation to the second well. The LOCOS layer is removed, and an impurity of the first conductivity type is introduced to part of the second well, thereby forming a third well in the second well. A field effect transistor is formed in each of said first, second and third wells, by a process including: (1) after introducing an N-type and P-type impurity in predetermined areas of the semiconductor substrate, forming a LOCOS layer in a predetermined pattern on the semiconductor substrate to form N-type and P-type low-density impurity layers in the predetermined areas under the LOCOS layer, part of the LOCOS layer being formed at least around a gate insulating layer of the field effect transistor; (2) forming a gate electrode; and (3) forming a high-density impurity layer comprising a source/drain area.
Another embodiment relates to a semiconductor device including a silicon substrate having a first conductivity type. The device includes a first well of the first conductivity type in the substrate, a second well of a second conductivity type adjacent to the first well in the substrate, and a third well of the first conductivity type formed within a portion of the second well, wherein the third well is electrically isolated by the second well. The device also includes a first field effect transistor formed in the first well. The first field effect transistor includes a first gate insulating layer provided in the first well, a first gate electrode on the first gate insulating layer, a first offset LOCOS layer outside of the first gate insulating layer, a first offset impurity layer comprising a low density impurity layer of the second conductivity type formed under the first offset LOCOS layer, and a first high density impurity layer of the second conductivity type provided outside the first offset LOCOS layer to serve as source/drain areas. The device also includes a second field effect transistor formed in the second well. The second field effect transistor includes a second gate insulating layer provided in the second well, a second gate electrode on the second gate insulating layer, a second offset LOCOS layer outside of the second gate insulating layer, a second offset impurity layer comprising a low density impurity layer of the first conductivity type formed under the second offset LOCOS layer, and a second high-density impurity layer of the first conductivity type provided outside the second offset LOCOS layer to serve as source/drain areas. The device also includes a third field effect transistor formed in the third well. The third field effect transistor includes a third gate insulating layer provided in the third well, a third gate electrode on the third gate insulating layer, a third offset LOCOS layer outside of the third gate insulating layer, a third offset impurity layer comprising a low density impurity layer of the second conductivity type formed under the third offset LOCOS layer, and a third high density impurity layer of the second conductivity type provided outside the third offset LOCOS layer to serve as source/drain areas. The device also includes a first LOCOS isolation layer electrically separating the first and second field effect transistors and a second LOCOS isolation layer electrically separating the second and third field effect transistors.
Still another embodiment relates to a method of manufacturing a semiconductor device, including forming a first well of a first conductivity type in a semiconductor substrate, forming a second well of a second conductivity type in the semiconductor substrate, and forming a third well within the second well, the third well having the first conductivity type. The third well is formed to be approximately ⅓ to approximately ½ the depth of the second well. A field effect transistor is formed in each of the first, second and third wells by introducing a low density impurity selected from the group consisting of an N-type impurity and a P-type impurity into predetermined areas of the semiconductor substrate, forming a LOCOS layer in a predetermined pattern on the semiconductor substrate, forming a gate electrode, and forming a high density impurity layer comprising a source/drain area. At least a portion of the LOCOS layer is positioned adjacent to and in contact with a gate insulating layer and the gate electrode.


REFERENCES:
patent: 5290714 (1994-03-01), Onozawa
patent: 1-268171 (1989-10-01), None
patent: 7-078881 (1995-03-01), None
patent: 8-274268 (1996-10-01), None

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