Method for forming self-aligned contacts using consumable...

Details Method for forming self-aligned contacts using consumable... Method for forming self-aligned contacts using consumable...

2001-05-07

2003-01-21

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000, C438S303000

Reexamination Certificate

active

06509229

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
BACKGROUND ART
In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structures typically include: a thin gate dielectric (tunnel oxide) layer formed on the surface of substrate overlying the channel region, a floating gate overlying the tunnel oxide, an interpoly dielectric overlying the floating gate, and a control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
A Flash EEPROM also includes peripheral portions which typically include input/output circuitry for selectively addressing individual memory cells.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gated structure, the source region and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of the memory cells. An etch stop or liner layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structures, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide such as such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
For miniaturization, it is desirable to dispose adjacent word lines as closely together as possible. One of the problems associated with the use of the nitride layer as an etch stop layer is that the effective separation between adjacent stacked gate structures is reduced. This is becoming critical as the separation between adjacent stacked gate structures diminishes.
A solution, which would allow further miniaturization of memory device without adversely affecting device performance or yield has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization continues at a rapid pace in the field of semiconductor, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for shrinking a semiconductor device by eliminating an etch stop layer so its stacked gate structures can be positioned closer together.
The present invention provides a method for shrinking a semiconductor device by eliminating an etch stop layer and replacing it with consumable second sidewall spacers so its stacked gate structures can be positioned closer together.
The present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact. In the formation of the contact opening, portions of the second sidewall spacers are removed. Therefore, unlike what happens in the conventional process in which the etch stop layer remains after the formation of the contact opening, portions of the consumable second spacers of the present invention are removed. Accordingly, with the present invention, adjacent multi-layer structures can be positioned closer together, thus permitting further miniaturization of devices.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5494838 (1996-02-01), Chang et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5763312 (1998-06-01), Jeng et al.

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