Method for making an embedded memory MOS

Details Method for making an embedded memory MOS Method for making an embedded memory MOS

2001-01-19

2003-01-21

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S258000, C438S275000, C438S532000

Reexamination Certificate

active

06509223

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method for forming an embedded memory MOS.
2. Description of the Prior Art
Due to continued process of integration, it is the present trend to produce semiconductor integrated circuits that simultaneously integrate a memory cell array and high-speed logic circuit elements onto a single chip. The result is the formation of an embedded memory which simultaneously combines a memory cell array and logic circuits, so as to save space and to enhance the speed of signal processing.
Please refer to
FIG. 1
to FIG.
8
.
FIG. 1
to
FIG. 8
are the cross-sectional schematic diagrams of making an embedded memory MOS on a semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a silicon substrate
16
, with a memory array area
12
and a periphery circuits region
14
defined on the silicon substrate
16
. The memory array area
12
further comprises a single cell-well
18
, and the periphery circuits region
14
further comprises a P-well
20
and a N-well
22
. Each well is isolated by a plurality of shallow trenches
11
.
As shown in
FIG. 1
, the method for forming an embedded memory MOS according to the prior art involves first forming a silicon oxide layer on the surface of the silicon substrate
16
via a thermal oxidation method, for use as a gate oxide layer
24
of each MOS. Thereafter, an undoped polysilicon layer
26
and an insulation layer
28
are formed, respectively, on the surface of the gate oxide layer
24
. Then as shown in
FIG. 2
, a photoresist layer
30
is formed in the periphery circuits region
14
as a hard mask, whereby a photolithographic and etching process (PEP) are used to etch both the insulation layer
28
and the undoped polysilicon layer
26
, located in the memory array area
12
, down to the surface of silicon oxide layer
24
.
After completely removing the photoresist layer
30
, as shown in
FIG. 3
, a doped polysilicon layer
32
, a silicide layer
34
, an insulation layer
36
and a silicon nitride layer
38
are formed, respectively, on the surface of the insulation layer
28
. As shown in
FIG. 4
, then a photoresist layer
40
is formed on the surface of the semiconductor wafer
10
, and a plurality of gate patterns
41
are defined in the photoresist layer
40
in the memory array area
12
, Thereafter, each of the gate patterns
41
are used as a hard mask to etch the silicon nitride layer
38
, the insulation layer
36
, the silicide layer
34
and the doped polysilicon layer
32
, located in the memory array area, down to the surface of the gate oxide layer
24
on the silicon substrate
16
. As a result, gates
41
of each MOS is formed in the memory array area
12
. Then, an ion implantation process is performed to form the lightly doped drains (LDD)
42
of each MOS in the memory array area.
After removing the photoresist layer
40
and the gate oxide layer
24
not covered by each of the gate
41
, as shown in
FIG. 5
, an insulation layer
44
is first formed on the surface of the semiconductor wafer
10
, whereby the thickness of the insulation layer
44
is greater than the total thickness of each layer in the periphery circuits region
14
. Then, the silicon nitride layer
38
in the periphery circuits region
14
is used as a stop layer in the proceeding chemical-mechanical polishing (CMP) process to horizontally align both the surfaces of the insulation layer
44
in the memory array area
12
and the silicon nitride layer
38
in the periphery circuits region
14
.
As shown in
FIG. 6
, the silicon nitride layer
38
, the insulation layer
36
, the silicide layer
34
, the doped polysilicon layer
32
and the insulation layer
28
, located in the periphery circuits region
14
, are etched down to the surface of the undoped polysilicon layer
26
. Then, a photoresist layer
46
is formed on the surface of the semiconductor wafer
10
, followed by a photolithographic process to define a plurality of gate patterns
47
of both the PNOS and MMOS in the photoresist layer
46
in the periphery circuits region
14
. Then, each of the gate patterns
47
in the photoresist layer
46
is used as a hard mask, with the insulation layer
44
in the memory array area
12
simultaneously acting as a hard mask to protect each of the gate
41
structure in the memory array area
12
, to etch the undoped polysilicon layer
26
in the periphery circuits region
14
down to the surface of the gate oxide layer
24
to form the gates
47
of the PMOS and NMOS. Then, an ion implantation process is performed to form the lightly doped drains(LDD)
42
of each PMOS and NMOS.
As shown in
FIG. 7
, a silicon nitride layer (not indicated) is formed on the surface of the semiconductor wafer
10
, followed by an anisotropic etching process to form a spacer
48
located on either side of each gate
47
in the periphery circuits region
14
. Next, two photolithographic processes followed by an ion implantation process of two different implantation areas are used to form a source
50
and a drain
52
of the NMOS and PMOS above the P-well
20
and N-well
22
in the periphery circuits region
14
.
Finally as shown in
FIG. 8
, a metal layer (not indicated) composed of Ti metal is sputtered on the surface of the semiconductor wafer
10
. Then, a rapid thermal process (RTP) with a temperature range of 500° C.~700° C. and a heating duration of approximately 30 seconds is used in order to allow the titanium atoms in the metal layer to diffuse into the surface of each source
50
, drain
52
and gate
47
in the periphery circuits region
14
. Then, a wet etching process is used to remove the unreacted metal layer on the surface of the semiconductor wafer
10
. A second rapid thermal process (RTP) with a temperature range of 700° C.~900° C. and a heating duration of approximately 30 seconds is used to form a self aligned silicide layer
54
on the surfaces of the source
50
, drain
52
and gate
47
in the periphery circuits area
14
.
The gate
41
in memory array area
12
is required to have a cap layer
38
in order to make the successive self-aligned contact(SAC) process proceed smoothly. However, a cap layer cannot be formed on the surface of the gates
24
in the periphery circuits region
14
. Thus, surface sheet resistance(Rs) of each source
50
, drain
52
and gate
47
in the successive self aligned silicide(salicide) process cannot be lowered. Therefore, in the prior art method for making the embedded memory MOS, repeated photolithographic and etching processes are needed to integrate the formation of gates in the memory array area and the periphery circuits region. The result is an increase in both process complexity and production cost, as well as a reduction in throughput.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of making an embedded memory MOS, so as to integrate the manufacturing process of the gates in both the memory array area and the periphery circuits region to simplify the manufacturing process.
The method according to the present invention involves first forming a first dielectric layer and an undoped polysilicon layer on the surface of semiconductor wafer with a defined memory array area and a periphery circuits region. Then, doping of the undoped polysilicon layer in the memory array area occurs, followed by the formation of a protective layer on the surface of the semiconductor wafer. Thereafter, a first photolithographic and etching(PEP) process is used to etch the protective layer and the doped polysilicon layer in the memory array area to form a plurality of gates, followed by the formation of a lightly doped drain(LDD) adjacent to each gate. Next, a silicon nitride layer and a second dielectric layer are formed on the surface of the semiconductor wafer, followed by the removal of the second dielectric layer, the silicon nitride layer and the protective layer. Finally, a second PEP is performed to etch the undopedpolysilicon layer in the periphery

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