Method for forming a memory integrated circuit

Details Method for forming a memory integrated circuit Method for forming a memory integrated circuit

1997-11-14

2003-09-09

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S640000, C438S657000

Reexamination Certificate

active

06617211

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to memory integrated circuits, and more specifically to dynamic random access memory integrated circuits.
BACKGROUND OF THE INVENTION
A dynamic random access memory integrated circuit (DRAM) provides temporary storage of digital information. A distinctive feature of the DRAM is that the information stored in the circuit is quickly lost unless it is refreshed. The reason that information storage is only temporary in a DRAM is that the data storage is in the form of a charged capacitor. The cell shown in
FIG. 1
is the heart of the memory circuit. It includes a word line
100
and bit line
102
connected to a pass transistor
104
and a capacitor
106
. When the voltage on the word line
100
is raised, the pass transistor
104
turns on and the bit line
102
is connected to the storage capacitor
106
. The information stored in the cell corresponds to whether the storage capacitor is charged or discharged. Unfortunately, capacitors leak charge and if not refreshed, the cell containing information corresponding to a charged capacitor would soon contain information corresponding to a discharged capacitor.
A natural solution to the problem of charge leakage is simply to increase the size of the capacitor. This approach, however, runs counter to the constant need for a smaller cell size, since in many DRAM circuits the storage capacitors alone can occupy as much as fifty to sixty percent of the die area of the circuit. The high premium placed on die area has resulted in cell designs in which the storage capacitor is formed not on the substrate surface, but instead on a protrusion that extends above the substrate surface. Such vertically-formed capacitors are known in the industry as a “stacked cell.” The use of a stacked cell allows for a higher storage capacitance without occupying precious semiconductor die area.
FIG. 2
a
shows a prior art planar DRAM cell and
FIG. 2
b
shows a prior art stacked cell. In
FIG. 2
a
the “storage node,” or the terminal of the capacitor connected to the transistor lies in the semiconductor substrate
200
beneath the capacitor dielectric
202
. The other terminal, or field plate, of the planar capacitor is typically polysilicon and is shown as element
204
. The wordline
206
comprises the gate interconnection for the pass transistor and lies over the gate dielectric
208
and between the source and drain implantation regions
210
. The bitline
212
runs perpendicularly to and over the wordline and storage capacitor. In the stacked cell shown in
FIG. 2
b
, both plates of the capacitor are polysilicon. The storage node
250
is convoluted and only contacts the substrate at transistor contact region
260
. The wordline
256
and bitline
262
are in essentially the same position as in the structure of
FIG. 2
a
. The capacitor dielectric
252
is typically oxide or a combination of oxide and nitride. The field plate
254
conforms to the convolutions of the storage node
250
to create a capacitor with a larger surface area than with the capacitor of
FIG. 2
a
. The drastically reduced die area occupied by the stacked cell of
FIG. 2
b
is also apparent in a comparison with the structure of
FIG. 2
a.
Designers of future generations of DRAMs demand that the storage capacitor occupy even less die area than that of the structure shown in
FIG. 2
b
. One problem with conventional processes for forming stacked cell capacitors is that the vertical nature of the capacitor requires relatively thick layers (typically oxide) for the capacitor's formation. Contact from the capacitor to the contact region (source or drain) of the pass transistor is complicated by the thick layers since the area of contact is often less than 0.5 &mgr;m in dimension, and will continue to be made smaller in future DRAM generations. Forming such a small opening in thick layers is very difficult and is a source of process complexity. For example, conventional processes rely on polysilicon or silicon nitride hardmasks with openings of about 0.36 &mgr;m to gain the selectivity necessary for etching such small holes in thick layers of oxide. Even using such a hardmask, the etch depth that can be achieved is often only about 1.0 &mgr;m when a depth of approximately 50% or greater is desired. To achieve the needed depth, prior processes typically rely on multiple masking steps where the bottom portion of the capacitor contact to the transistor is formed before the thick oxide layers are applied. The hole is then plugged with polysilicon and the thick layers necessary for forming the upper portions of the capacitor follow. The multiple mask steps necessary to form the capacitor in prior processes are thus complicated and economically unattractive. The present invention provides a simpler approach to the formation of stacked capacitors.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, there is disclosed herein a process for fabricating a memory integrated circuit. The process addresses the difficulties involved in forming a stacked-cell or crown-cell capacitor that is used in a dynamic random access memory circuit. In particular there is disclosed a process including the step of forming a contact region (typically at the source or drain of a transistor) in a semiconductor material structure, that is, in a structure comprising a semiconductor substrate and any material subsequently applied to the substrate. The semiconductor material structure, with the exception of the contact region, is covered with a first material, and the first material and the contact region are then covered with a layer of a second material. The portion of the second layer covering the contact region is removed to expose the contact region such that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer over the first conductive layer, and forming a second conductive layer over the dielectric layer.
Further in accordance with the principles of the present invention, there is disclosed herein an integrated circuit including a cavity in a multilayer material structure, the cavity including a lower region having a bottom at a contact region and a top having a first width, the cavity further including an upper region having a greater width than the first width. The circuit also includes a first conductive layer formed in the cavity to contact the contact region and to conform to the lower and upper regions of the cavity. A layer of dielectric is formed over the first conductive layer, and a second conductive layer is formed over the dielectric layer.
An advantage of the present invention is that a stacked capacitor can be fabricated with a single etch step rather than with the typical two etch steps.


REFERENCES:
patent: 5346844 (1994-09-01), Cho et al.
patent: 5478768 (1995-12-01), Iwasa
patent: 5801079 (1998-09-01), Takaishi
patent: 5933724 (1999-08-01), Sekiguchi et al.
patent: 5972747 (1999-10-01), Hong
Stanley Wolf Ph.D. in Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattics Press, pp. 274 and 275, Jan. 1990.

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