Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-24
2003-01-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S257000, C438S250000
Reexamination Certificate
active
06503791
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device of the type in which an electrode of a capacitor or a plug of each memory cell is formed by chemical vapor deposition, and to a method of manufacturing the semiconductor device.
High integration density of semiconductor devices such as dynamic random access memories (DRAMs) can be achieved when a cell area is reduced. This means that an occupying area of the capacitor of the memory cell decreases inevitably. Nonetheless, predetermined storage capacitance necessary for reading out the memory must be secured to prevent a soft error. In other words, means is necessary for increasing storage capacitance per unit area to attain a high integration density of semiconductor devices. One of such means would be the one that applies an oxide dielectric material having a large specific dielectric constant to a capacitor insulating film. A Ta
2
O
5
film (specific dielectric constant: 20 to 25) has been used at present for the capacitor insulating film in place of a SiO
2
film (specific dielectric constant: 3.8) and a Si
3
N
4
film (specific dielectric constant: 7 to 8) that have been used in conventional memories. In memories of a giga-bit scale, however, storage capacitance necessary for readout is not sufficient even when the Ta
2
O
5
film having a large specific dielectric constant is used and capacitors have a three-dimentional structure to increase a substantial capacitor area. Therefore, oxide dielectric materials having a specific dielectric constant of 100 or more, such as strontium titanate: SrTiO
3
(STO), Barium Strontium Titanate: (Ba,Sr)TiO
3
(BST), lead zirco-titanate: Pb(Zr, Ti)
3
(PZT) and SrBi
2
Ta
2
O
9
(SBT), have been examined for a capacitor dielectric film. PZT and SBT among them can be applied to ferroelectric memories that utilize their ferroelectricity.
To improve electric property (dielectric property), these oxide dielectric materials require film formation and post heat-treatment at a high temperature of at least 400° C. to 700° C. in an oxidizing atmosphere. In this instance, when a lower electrode is oxidized by oxygen contained in the atmosphere, an insulating film having a lower dielectric constant than that of a capacitor insulating film is formed, inviting the substantial drop of capacitance of the capacitor.
When a barrier layer and plugs positioned below the lower electrode are oxidized, electric conduction is lost between the transistor and the capacitor. Therefore, platinum (Pt) that is relatively stable in a high-temperature oxidizing atmosphere and ruthenium (Ru) and iridium (Ir) that keep conduction even when oxides are formed have been examined as promising materials of the lower electrode. Most preferred among them is Ru as the lower electrode of the oxide dielectric material because it has high fine etching property.
To sum up, storage capacitance necessary for readout might be insufficient in giga-bit scale memory cells even when an oxide dielectric material having a high specific dielectric constant is used because the area the capacitor can occupy is small. To substantially increase the capacitor area, therefore, the capacitor structure must be rendered three-dimentional. For example, process steps are necessary to shape the lower electrode of the capacitor into a three-dimentional structure and then to form the oxide dielectric material of the capacitor, or to shape the lower electrode on the three-dimentional structure that is formed in advance, and then to form the oxide dielectric material.
The article entitled “(Ba, Sr)TiO
3
Capacitor Technology for Gigabit Scaled DRAMs” in “Technical Digest of International Electron Devices and Materials (IEDM)”, 98, pp. 803-806, describes an example of a three-dimentional structure of a capacitor that uses BST as the material of a dielectric film, shapes electrodes into a convex shape and uses Ru as the material of the electrodes.
The article entitled “Low Temperature (Ba, Sr)TiO
3
Capacitor Process Integration (LTB) Technology for Gigabit Scaled DRAMs” in “Technical Digest of International Electron Devices and Materials (IEDM)”, 99, pp. 789-792 describes an example of a three-dimentional structure of a capacitor that uses BST as a material of a dielectric film, shapes electrodes into a concave shape and uses SrRuO
3
as the material of the. electrodes.
Furthermore, the article entitled “Development of Ru/Ta
2
O
5
/Ru Capacitor Technology for Gigabit Scale DRAMs” in “Technical Digest of International Electron Devices and Materials (IEDM)”, 99. pp. 793-796 teaches to sputter and etch away unnecessary Ru in a formation step of a lower electrode of a capacitor made of Ru.
However, none of the references cited above recognize the following problems. In other words, these references do not teach or suggest at all the technical features of the present invention that will be explained below in detail.
SUMMARY OF THE INVENTION
Studies conducted by the inventors of the present invention have revealed that the following problems develop when a capacitor having a three-dimentional structure is fabricated by using the prior art technologies described above.
The three-dimentional structure of the lower electrode fabricated and examined by way of experiment by the present inventors will be explained with reference to
FIGS. 1
a
to
1
c.
All the drawings depict the section. First, a Ru lower electrode film
5
′ having a film thickness of 400 nm is deposited on plugs
1
made of Ru and a plug interlayer insulating film
2
made of SiO
2
, for example (
FIG. 1
a
). The lower ruthenium electrode film
5
′ is then etched into a cylinder shape, an elliptic cylinder shape or a rectangular shape to the surface of the plug interlayer insulating film
2
by known photolithography and dry etching, giving lower electrodes
5
having a three-dimentional structure (
FIG. 1
b
). In a giga-bit scale semiconductor device having a minimum feature size of not greater than 0.15 &mgr;m, however, it is difficult to vertically etch the ruthenium electrode having the shape described above. Therefore, the etching shape becomes such that bottom portion becomes wider than the top portion as shown in
FIG. 1
b.
After the lower ruthenium electrode
5
is etched, an oxide dielectric material
6
made of BST, for example, is deposited by chemical vapor deposition (CVD). An upper electrode
7
made of Ru, for example, is then deposited by CVD, completing the capacitor (
FIG. 1
c
). In this case, since the bottom portion of the lower electrode has a wide patterning shape as described above, the adjacent capacitors are so close to each other that electric interaction occurs between them. When a sufficient gap is secured between the bottom portions of the electrodes, a sufficient area of the top surface cannot be secured, on the contrary, and the sectional shape of the electrode becomes triangular with the result that the surface area of the three-dimentional electrode decreases.
Another structural example of a three-dimentional structure fabricated and examined by the present inventors by way of experiment, in which holes are formed into a silicon oxide film, fine patterning of which is easy, from the film surface, and a Ru lower electrode is then deposited by CVD, will be explained with reference to
FIGS. 2
a
to
2
c.
All the drawings show the section. First, a 400 nm-thick capacitor interlayer insulating film
3
made of SiO
2
, for example, is deposited by CVD on plugs
1
made of Ru and a plug interlayer insulating film
2
made of SiO
2
, for example. Holes reaching the surface of the plug interlayer insulating film
2
are then formed in the capacitor interlayer insulating film
3
into a cylinder shape, an elliptic cylinder shape or a rectangular shape, by known photolithography and dry etching. Lower ruthenium electrodes
5
′ having a film thickness of 30 nm are thereafter deposited by CVD, giving the lower electrodes having the three-dimentional structure (
FIG. 2
a
). However, it is necessary in this case to remove the portion of t
Hiratani Masahiko
Matsui Yuichi
Nabatame Toshihide
Nakamura Yoshitaka
Shimamoto Yasuhiro
Mattingly Stanger & Malur, P.C.
Nelms David
Tran Long
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