Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-17
2003-04-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000
Reexamination Certificate
active
06541322
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a metal-oxide semiconductor (MOS) transistor, and more particularly, to a method of preventing gate depletion effects occurring in the MOS transistor.
2. Description of the Prior Art
With the development of very large scale integration (VLSI), the low electricity consumption and high integration of metal-oxide-semiconductor (MOS) transistors allows them to be widely applied in the semiconductor process. Usually, a MOS transistor comprises a gate and two semiconductor regions, called a source and drain located on each side of a capacitor with an electrical characteristic opposite to that of the silicon substrate. The major structure of the gate is composed of a gate oxide layer and a gate conductive layer. When a proper bias is added to the gate, the MOS transistor can be regarded as a solid switch to control the connection of current.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are schematic diagrams of fabricating a MOS transistor according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprises a silicon substrate
12
and plurality of both field oxides
14
and channel stops
16
. In the prior art, the fabricating technique of the MOS transistor first involves placing the semiconductor wafer
10
in a furnace, followed by injecting oxygen into at atmospheric pressure. Thus, by using dry oxidation, the single crystal silicon on the surface of the active area is oxidized to become a silicon oxide layer
18
with a thickness of 100-250 angstroms. The silicon oxide layer
18
is used as a gate oxide.
A low-pressure CVD (LPCVD) process is then performed to deposit an undoped polysilicon layer
20
, with a thickness of 1000-2000 angstroms, on the surface of semiconductor wafer
10
to function as a gate conductive layer. After the formation of the undoped polysilicon layer
20
, a patterned photoresist layer
22
is formed on the surface of the undoped polysilicon layer
20
to define the pattern and the position of a gate. As shown in
FIG. 2
, the pattern of the photoresist layer
22
is used as a hardmask to perform an anisotropic etching process to remove both the undoped polysilicon layer
20
and the silicon oxide layer
18
uncovered by the hardmask down to the surface of the silicon substrate
12
. Then, the photoresist layer
22
is removed to complete the formation of a gate
24
.
As shown in
FIG. 3
, a silicon nitride (Si
3
N
4
)
26
is deposited on the surface of the semiconductor wafer
10
. As shown in
FIG. 4
, an anisotropic etching process is then used to form a spacer
28
on either side of the gate
24
. Finally, an ion implantation process is performed, using the spacer
28
as a mask, to form a source
32
and drain
34
of the MOS transistor and complete the fabrication of the MOS transistor. The distance L between the source
32
and drain
34
is the channel length. The undoped polysilicon layer
20
comprising the gate
24
is implanted as a doped polysilicon layer during the ion implantation process performed for forming a source and a drain of each PMOS and NMOS transistor.
After performing the ion implantation process, an annealing process is performed to uniformly diffuse dopants in the undoped polysilicon layer
20
and to simultaneously drive dopants into the source
32
and drain
34
. Gate depletion effects occur when the annealing process insufficiently drives the dopants down the entire depth of the gate
24
. As shown in
FIG. 5
, a portion of the gate nearest the gate oxide layer
18
is depleted of dopants and behaves as an insulating region
30
. As a result, the MOS transistor behaves as though the gate oxide layer
18
is substantially thicker, thereby resulting in signal delay of the gate and a substantial degradation in device performance.
Various techniques have been proposed to reduce gate depletion effects, the simplest method is to increase implantation dosage. However, because of the poly grain boundaries and the different dopant segregation at the poly/SiO2 interface, increasing the implant dose not necessarily increase the dopant concentration proportionally. Also, unless the gate oxide layer has good resistance to boron penetration, increasing the boron dose usually results in a boron penetration effect of a PMOS transistor.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for preventing gate depletion effects occurring in the MOS transistor to solve the above-mentioned problem.
In the preferred embodiment, the method is first forming a silicon oxide layer on the substrate of a semiconductor wafer. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si
1-x
Ge
x
, x=0.05~1.0) layer on the amorphous silicon layer. Thereafter, an etching process is performed to remove portions of the silicon germanium layer and the amorphous silicon layer to form a gate of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.
The present invention method uses a silicon germanium layer and an amorphous silicon layer as a gate conductive layer of the MOS transistor so as to increase active dopant concentration in the conductive layer and inhibit gate depletion effects.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4521794 (1985-06-01), Murase et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 6281559 (2001-08-01), Yu et al.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, 1986, pp. 323-324.
Hsu Winston
Lattin Christopher
Macronix International Co. Ltd.
Niebling John F.
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