Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-09
2003-04-22
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000
Reexamination Certificate
active
06551884
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device including gate insulation films having different thicknesses. The present invention also relates to a method for forming such a semiconductor device.
(b) Description of the Related Art
Along with the developments of finer patterning and high-speed operation of semiconductor devices, a multi-functional semiconductor device, such as a system LSI, formed on a single semiconductor substrate is increasingly used for a variety of applications. In the system LSIs, a finer patterning technology using a STI (shallow trench isolation) structure is generally used. On the other hand, some techniques for the system LSIs use a fabrication process for forming gate insulation films having different film thicknesses for adapting the gate insulation films to different functions of the system LSIs.
In a typical STI structure, a problem of the step portion in the STI, known as a STI step problem, is known. The STI step is formed as detailed below. In general, a silicon oxide film formed within the shallow trench is subjected to an undesired etching during the etchings performed in the respective areas isolated by the shallow trench. The undesired etching generally causes a depression at the edge of the shallow trench, which forms the STI step. Once the STI step is formed at the edge portion of the isolation trench, the MOSFETs separated by the shallow trench suffer from an increase in the off-leakage current, whereby transistor characteristics are degraded. Patent Publication JP-A2000-195969 describes a technique for preventing the degradation of the transistor characteristics by forming MOSFETs including gate insulation films having different thicknesses on a single substrate.
FIGS. 1A
to
1
K show the consecutive steps of fabrication of such gate insulation films.
On a silicon (semiconductor) substrate
20
, a silicon oxide film
21
is formed by a thermal oxidation technique, followed by deposition of a silicon nitride film
22
thereon, as shown in
FIG. 1A
, by using a CVD technique. On the silicon nitride film
22
, a photoresist pattern (not shown) is formed, which has openings on the area for forming the shallow trench, by using a photolithographic technique. The silicon nitride film
22
is then subjected to patterning by anisotropic etching using the photoresist pattern as an etching mask, as shown in FIG.
1
B. By using the thus patterned silicon nitride film
22
as an etching mask, the silicon oxide film
21
and the top portion of the silicon substrate
20
are selectively etched to form a shallow trench or isolation trench
23
having a depth of 100 to 500 nanometers (nm), as shown in FIG.
1
C. The depth of the shallow trench
23
depends on the types of the circuit to be formed on the silicon substrate
20
.
Subsequently, a silicon oxide film
24
having a thickness of around 300 to 1000 nm is deposited on the silicon nitride film
22
and within the shallow trench
23
by using a low-pressure CVD (LPCVD) technique. A CMP (chemical-mechanical polishing) process is then performed on the wafer by using the silicon nitride film
22
as a stopper, to remove a portion of the silicon oxide film
24
above the silicon nitride film
22
, thereby leaving the lower portion of the silicon oxide film
24
within the shallow trench
23
. Thereafter, the silicon nitride film
22
is removed by wet etching using hot phosphoric acid, as shown in FIG.
1
D.
Subsequently, a silicon oxide film
25
having a thickness of around 3 to 15 nm is formed on the surface portion of the silicon substrate
20
by using a thermal oxidation technique, as shown in FIG.
1
E. Then, an ion implantation process is conducted for selectively implanting impurity ions such as boron or boron fluoride into an nMOS area, wherein nMOSFETs are to be formed, by using a mask, separately from an ion implantation process for implanting impurity ions such as phosphorous or arsenic into a pMOS area, wherein pMOSFETs are to be formed, by using another mask. Thus, well regions (not shown) are formed in the respective areas of the silicon substrate
20
.
Thereafter, a silicon nitride film
26
is formed on the silicon oxide film
25
, followed by forming a photoresist pattern
30
having an opening on a memory cell array area
29
among the whole areas including an logic circuit area
27
, a sense amplifier area
28
and the memory cell array area
29
, the memory cell array area
29
generally including MOSFETs having a larger thickness for the gate oxide films. The silicon nitride film
26
exposed from the opening of the photoresist pattern
30
is removed by etching, as shown in FIG.
1
F. Further, ion-implantation is conducted for implanting impurity ions such as boron or boron fluoride through the opening of the photoresist pattern
30
while passing the thin silicon oxide film
25
, thereby forming channel regions of memory cells in the memory cell array area
29
.
The photoresist pattern
30
is then removed, followed by forming another photoresist pattern
31
having an opening on the sense amplifier area
28
. The sense amplifier area
28
includes MOSFETs which have a gate insulation film having a thickness similar to the thickness of the gate insulation film of the MOSFETs in the memory cell area
29
, and a threshold voltage different from the threshold voltage of the MOSFETs in the memory cell area
29
. By using the photoresist pattern
31
as a mask, the silicon nitride film
26
in the sense amplifier area
28
is selectively removed, followed by implantation of impurity ions such as boron through the opening of the photoresist pattern
31
and the thin silicon oxide film
25
, to form channel regions of the MOSFETs in the sense amplifier area
28
, as shown in FIG.
1
G.
The photoresist pattern
31
is then removed, followed by wet etching using the silicon nitride film
26
as a mask and hydrofluoric acid as an etchant, to remove the silicon oxide film
25
in the sense amplifier area
28
and the memory cell array area
29
, which may be called herein thick-film areas. Another silicon oxide film
32
having a larger thickness than the silicon oxide film
25
in the logic circuit area
27
is then formed as a gate insulating film in the sense amplifier area
28
and the memory cell array area
29
by using an oxidation process, as shown in FIG.
1
H. As shown in
FIG. 1H
, the silicon oxide film
25
and the silicon nitride film
26
are formed on the logic circuit area
27
, which may be called herein a thin-film area, whereas the silicon oxide film
32
is formed on the thick-film areas
28
and
29
.
By using hot phosphoric acid as an etchant, the silicon nitride film
26
is removed in the logic circuit area
27
, followed by forming another photoresist pattern
33
covering the active areas of the pMOSFETs in the thin-film area
27
and the thick-film areas
28
and
29
. By using the another photoresist pattern
33
as a mask, impurity ions such as boron or boron fluoride are implanted into the active areas of the nMOSFETs in the logic circuit area
27
to form channel regions in the nMOSFETs in the logic circuit area
27
. Similarly, by covering the active areas of the nMOSFETs in the thin-film area
27
and the thick-film areas
28
and
29
, impurity ions are implanted to the active areas of the pMOSFETs in the logic circuit area
27
, to form channel regions of the pMOSFETs therein. Thereafter, the silicon oxide film
25
in the logic circuit area
27
is removed, as shown in
FIG. 11
, followed by removal of the another photoresist pattern
33
.
A silicon oxide film
34
having a thickness of about 4 to 7 nm is then formed as a gate insulating film in the logic circuit area
27
by thermal oxidation, as shown in FIG.
1
J. In this step, the silicon oxide film
34
is also formed on the preceding silicon oxide film
32
in the thick-film areas, or the sense amplifier area
28
and the memory cell array area
29
, whereby all the channel regions and the gate insulating films are formed in the
Cao Phat X.
Le Thao X.
McGinn & Gibb PLLC
NEC Electronics Corporation
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