Method of fabricating NROM memory cell

Details Method of fabricating NROM memory cell Method of fabricating NROM memory cell

2002-06-25

2003-07-29

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S269000

Reexamination Certificate

active

06599801

ABSTRACT:

FIELD OF THE INVENTION
The invention relates in general to a method of fabricating nitride read-only memory (NROM) cells, and more particularly to a method of fabricating a discrete NROM cell without a BD oxide.
DESCRIPTION OF THE RELATED ART
Memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), flash EEPROM, and nitride read-only memory (NROM). These advanced memory devices can accomplish the tasks that ROM can't do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
FIG. 1A
is a cross-sectional view of conventional NROM cells. The substrate
10
is implanted with a source
12
and a drain
14
. On top of substrate
10
lies a sandwiched structure having a nitride layer
17
between a top oxide layer
16
and a bottom oxide layer (tunneling oxide layer)
18
, known as an ONO structure. A number of BD (barrier diffusion) oxides
20
are formed to isolate the adjacent ONO structures and form the channels
22
. The structure of an NROM cell which contains dual bits in one cell is also depicted in FIG.
1
A. The larger region (encircled with the dashed line) denotes an NROM cell
30
, and the two smaller regions encircled with the dashed lines denote the first bit
32
and the second bit
34
.
The NROM device generally includes a memory array and a peripheral portion. In the conventional process, the memory array is fabricated before the peripheral portion of the NROM cell. First, the ONO layer is added over the entire array, after which the ONO layer is etched according to a predetermined pattern. The source/drain is then implanted, and the buried drain (BD) is formed. Following the fabrication of the memory array, the peripheral portion is implanted and the well is formed. The ONO layer over the peripheral portion is removed, after which the oxide is grown on top of the BD, so as to form the BD oxide. Following the oxidation in the peripheral portion, the polysilicon is deposited over the ONO layer of the memory array and the BD oxide.
However, there are several drawbacks in the conventional fabricating method. For example, the NROM cell with multiple oxide layers may have buried diffusion problems, as shown in FIG.
1
B. In the conventional process, the phosphorus or arsenic ions are implanted and the source
12
and drain
14
are originally kept at a distance of d. After the second oxide layer is grown on the first oxide layer, the source
12
and drain
14
diffuse and the distance between thereof is d′, as the dash lines
12
′ and
14
′ depicts. Similarly, the source
12
′ and drain
14
′ diffuse (as depicted by dash lines
12
″ and
14
″) and the distance between thereof is d″ if a third oxide layer is grown on the second oxide layer. According to the description, it is clear that the BD over-diffusion problem can shorten the length of the channel. Additionally, after the deposition of the oxide layer, the end of the ONO layer
36
close to the sidewall is easy to expand. Due to the existence of BD oxide, the end of the ONO layer
36
warps upward, as shown in FIG.
1
C. In this situation, it is very possible that the silicon nitride layer (middle layer of the ONO layer
36
) touches the polysilicon layer after the polysilicon layer
24
is added on. The NROM device will have poor reliability if silicon nitride contacts with the polysilicon. Also, for the NROM device that required multiple layers of oxide, the top oxide layer is going to be exposed to the cleaning solution several times in the cleaning procedure. The oxide layer will thus become thinner and have a poor quality.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating an NROM memory cell, so that the problems such as top oxide loss, touching between nitride and polysilicon, and BD over-diffusion can be solved.
The invention achieves the above-identified objects by providing a method of fabricating NROM memory cell, wherein the NROM memory cell comprises a memory array and a peripheral portion. The fabricating method comprises the steps of: providing a substrate which an oxide layer formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array stacking gate structure.


REFERENCES:
patent: 6436778 (2002-08-01), Fang et al.

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