Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2000-02-04
2003-07-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S758000, C438S239000, C438S243000, C438S244000, C438S245000, C438S250000, C438S253000, C257S068000, C257S071000
Reexamination Certificate
active
06589885
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and method of manufacture, and particularly, the present invention relates to a semiconductor memory device having a capacitor which includes a silicon layer having introduced impurities therein, and to a method of manufacturing such a semiconductor memory device.
BACKGROUND OF THE INVENTION
In a semiconductor device, a silicon layer is used in various portions, such as a conductive layer, a resistant element, a gate electrode of transistor, and a capacitor of a memory cell. As is well known, in a Dynamic Random Access Memory (DRAM), a capacitor of the memory cell is comprised of a silicon layer. The silicon layer composes a storage electrode and a cell-plate electrode of the capacitor. A method for manufacturing such capacitors of the DRAM is shown in Japanese Laid Open Patent “Toku-Kai-Hei 7-235616”, which was published on Sep. 5, 1995.
In the DRAM of the publication, the silicon storage electrode of the capacitor is composed of a polycrystalline silicon layer and an amorphous silicon layer. Generally, if the silicon layers are applied as the conductive layers, the silicon layers are introduced with an impurity having a high concentration in order to reduce the resistance and maintain good conduction therein. In the polycrystalline silicon layer of the publication, which is connected to diffusion regions (source or drain of transistors) formed in a semiconductor substrate, a conductive impurity having a deep concentration is introduced therein.
In heat treatment processes after forming the storage electrode including the silicon layer which is introduced with the deep impurity, the impurity in the silicon layer is frequently diffused in the semiconductor substrate. The diffused impurity influences an impurity concentration of the diffusion region (source or drain) formed below the storage electrode. Also, the diffused impurity brings an unexpected extension of the diffusion region during the heat treatment after forming the storage electrode.
Therefore, the characteristics of the transistors, typically a threshold voltage of the transistor, is changed to unexpected results.
If an excess of the impurity is introduced into the silicon layer, the impurity can easily diffuse into the semiconductor substrate. As above, the characteristics of the transistors are then influenced.
The smaller the size of the DRAM, the more significant is the leakage current that occurs under a field oxidation layer. Such diffusing of the impurity accelerates the leakage current. Therefore, the date-retention-time may be shorten to less than a predetermined desired date-retention-time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which is capable of reducing adverse influences to characteristics of the transistor and securing a predetermined data-retention-time.
Another object is to provide a method of manufacturing such semiconductor device without the addition of many process steps.
To achieve the objects, in a semiconductor device having a silicon, the silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer, wherein a concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.
According to the present invention, a semiconductor device is realized which is capable of reducing changes in characteristics of the device.
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Lee Granville
Oki Electric Industry Co. Ltd.
Smith Matthew
Volentine & Francos, PLLC
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