Nonvolatile semiconductor memory device and data...

Details Nonvolatile semiconductor memory device and data... Nonvolatile semiconductor memory device and data...

2001-11-14

2003-04-29

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189050, C365S189020, C365S221000, C365S042000

Reexamination Certificate

active

06556504

ABSTRACT:

RELATED APPLICATION
This application claims priority upon Korean Patent Application No. 2001-00346, filed on Jan. 4, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device. More specifically, the present invention is directed to a nonvolatile semiconductor memory device capable of changing a column address while inputting/outputting a data column to/from the memory device and method for controlling data input/output thereof.
BACKGROUND OF THE INVENTION
A rewritable nonvolatile semiconductor memory device, such as, a NAND-type flash memory device, has an array of strings formed from a plurality of memory cells that are serially connected between a string selection transistor and a ground selection transistor. In a writing (or programming) operation of the NAND-type flash memory device, as shown in
FIG. 15
, when signal of a data input command, successive column and row addresses for assigning memory cells are inputted. And, specific-unit data is synchronized with a successive low-to-high transition of a write enable signal {overscore (WE)}, as a data input signal, and is successively inputted through input/output pins I/Oi (i=0-7). The inputted data is temporarily stored in latches of a register or a page buffer circuit. Thereafter, the temporarily stored data is programmed. In a read operation of the NAND-type flash memory device, as shown in
FIG. 16
, upon a read command, successive column and row addresses for assigning memory are inputted. And then, data of the assigned column and row addresses is read or sensed during a low interval of an R/{overscore (B)} signal. The sensed data is temporarily stored in latches of a register or a page buffer circuit that is located in the memory device. Finally, specific-unit data stored in the register is synchronized with a successive high-to-low transition of a read enable signal {overscore (RE)}, as a data output signal, and is successively outputted through the input/output pins I/Oi (i=0-7).
In the NAND-type flash memory device, the specific-unit is conventionally called “page”. The NAND-type flash memory device can be applied to a solid-state file storage, a digital voice recorder, a digital still camera or a portable system that needs nonvolatility. The NAND-type flash memory device can operate reading and programming operations at higher speed by expanding the number of memory cells to be sensed/programmed at the same time or expanding a page size to improve reading or programming speed per 1-byte.
FIG. 17
schematically illustrates a flash memory system, which includes a host
10
, a memory controller
20
, and an NAND-type flash memory device
30
. The memory controller
20
includes a control unit
22
and a buffer memory
24
. The buffer memory comprises a first data storage area (A) having 2 KB storage capacity and a second data storage area (B) having 64 B storage capacity. The NAND-type flash memory device
30
is controlled by a memory controller
20
, and includes a memory cell array and a page buffer circuit
36
or a register. The memory cell array is divided into a main field array
32
and a spare field array
34
. Normal data is stored in the main field array
32
, while additional data information associated with the normal data is stored in the spare field array
34
. The additional data information includes error correction and detection code (ECC) data, address mapping data, and wear levelling data. If a page size of the NAND-type flash memory device is “2 KB+64 B”, memory cells corresponding to 64 B occupy one page of the spare field array
34
. The use of wear levelling data is described in U.S. Pat. No. 5,568,423 entitled “FLASH MEMORY WEAR LEVELLING SYSTEM PROVIDING IMMEDIATE DIRECT ACCESS TO MICROPROCESSOR”.
For example, when a size of a page being a specific-unit of a writing or reading operation in a memory device is “2 KB+64 B”, 2 KB is allocated to store normal data, and 64 B is allocated to additional data. If a writing operation of the flash memory device is performed in the memory system shown in
FIG. 17
, the host
10
sequentially transmits normal data of 2 KB to the memory controller
20
with a unit of 512 B. The memory controller
20
temporarily stores the transmitted normal data of 2 KB in the first data storage area (A) of the buffer memory
24
. A control unit
22
of the memory controller
20
generates additional data of 64 B, in which the additional data has error correction and detection code data, address mapping data, and wear levelling data by using the stored normal data of 2 KB in the first data storage area (A). Also, the control unit
22
temporarily stores the generated additional data in the second data storage area (B) of the buffer memory
24
.
The memory controller
20
sequentially transfers normal data of 2 KB to the memory device, based upon an input/output structure of an NAND-type flash memory device. The NAND-type flash memory device
30
temporarily stores the sequentially transferred normal data of 2 KB in a page buffer area of 2 KB corresponding to the main field array
32
. Thereafter, the memory controller
20
sequentially transfers additional data of 64 KB to the memory device, based upon the input/output structure of the NAND-type flash memory device. The NAND-type flash memory device
30
temporarily stores the sequentially transferred additional data of 64 B in a gate buffer area of 64 B corresponding to the spare field array
34
. After completely inputting the “2 KB+64 B” data, the data stored in the page buffer
36
or the register based upon the input of a program instruction is programmed at the same time.
FIG. 18
schematically illustrates another memory system having a flash memory device. in the system of
FIG. 18
, a memory controller
20
has a buffer memory
24
′ that is smaller than a page size of a NAND-type flash memory device
30
′. The buffer memory
24
′ includes of a first data storage area (A′) of 512 B for storing normal data and a second data storage area (B′) of 16 B for storing additional data. The NAND-type flash memory device
30
′ has the same page size of“2 KB+64 B” as that shown in
FIG. 17
, and is controlled by a memory controller
20
′. When a NAND-type flash memory device having a page size larger than a buffer memory
24
′ of the memory controller
20
′ is applied to the system, the following problem occurs.
If a writing operation of a flash memory device is performed in a memory system as shown in
FIG. 18
, a host
10
′ transfers normal data of 512 B to a memory controller
20
′. The memory controller
20
′ temporarily stores the transferred normal data of 512 B in a first data storage area (A′) of a buffer memory
24
′. By using the stored normal data of 512 B, a control unit
22
′ of the memory controller
20
′ generates additional data of 16 B that includes error correction and detection code data, address mapping data, and wear leveling data. Also, the control unit
22
′ temporarily stores the generated additional data in a second data storage area (B′) of the buffer memory
24
′.
The memory controller
20
′ sequentially transfers normal data of 512 B to a NAND-type flash memory device, based upon an input/output structure of the memory device. The NAND-type flash memory device
30
′ temporarily stores the sequentially transferred normal data of 512 B in a page buffer circuit
36
′ and a register. Thereafter, the memory controller
20
′ sequentially transfers additional data of 16 B to the NAND-type flash memory device, based upon an input/output structure of the memory device. The NAND-type flash memory device
30
′ temporarily stores the sequentially transferred additional data of 16 B to the page buffer circuit
36
′ or the register. Since a page size of the NAND-type flash memory device
30
′

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