Methods of forming semiconductor structures

Details Methods of forming semiconductor structures Methods of forming semiconductor structures

2002-01-30

2003-04-01

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S689000, C438S721000

Reexamination Certificate

active

06541362

ABSTRACT:

TECHNICAL FIELD
The invention pertains to methods of forming semiconductor structures, including methods of forming transistor gates for field effect transistor and flash memory devices.
BACKGROUND OF THE INVENTION
A continuing goal in semiconductor device fabrication is to create increasing densities of circuitry on semiconductor real estate. Such goal is realized through ever-decreasing dimensions of semiconductor circuit elements. For instance, in the early 1970's a typical gate length of a field effect transistor gate in a dynamic random access memory (DRAM) device was on the order of from 5 to 6 micrometers, and polysilicon was utilized as a sole conductive material of the gate. Advances in DRAM generation of the late 1980's reduced the gate length to approximately one micrometer. However, it was found that word line resistance was too high if conductively doped polysilicon was utilized as the sole conductive component of a gate line, and accordingly silicide (such as tungsten silicide, molybdenum silicide or titanium silicide) was deposited over the polysilicon. The term “polycide” was coined to describe a stack of gate materials which comprised conductively doped polysilicon having a silicide thereover.
Technological advances of the 1990's reduced the gate length to less than 0.2 micrometers. It was found that the resistance of polycide materials was too high for such gates, and accordingly procedures were developed to provide a metal to replace the silicide of the polycide structure. Exemplary metals utilized are tungsten, molybdenum and titanium. Such gates would be considered modern structures in current technology.
FIG. 1
shows a semiconductor wafer fragment
10
comprising a field effect transistor
12
having such a gate structure. More specifically, wafer fragment
10
comprises a substrate
14
having a gate structure
16
formed thereover. Gate structure
16
comprises a gate oxide layer
20
(which typically comprises silicon dioxide), a conductively-doped-semiconductive-material layer
22
(which can comprise silicon and germanium, and which typically comprises conductively doped polysilicon), a conductive diffusion barrier layer
24
(which typically comprises a metal nitride, such as, for example, WN
x
, TiN), a metal layer
26
(which can comprise, for example, tungsten, molybdenum or titanium), and an insulative cap
28
(which can comprise, for example, silicon nitride or silicon dioxide).
Semiconductive substrate
14
can comprise, for example, conductively doped monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Gate structure
16
has opposing sidewalls
30
, and insulative spacers
32
are formed along such opposing sidewalls. Insulative spacers
32
can comprise, for example, silicon nitride.
Source/drain regions
18
formed proximate gate structure
16
, and a channel region
19
is defined beneath gate structure
16
. Spacers
32
can be utilized during formation of source/drain regions
18
to space an implant of a conductivity-enhancing dopant from sidewall edges
30
, and to thereby control a location of heavily doped source/drain regions
18
relative to sidewalls
30
. Lightly doped diffusion regions are formed beneath sidewalls
32
, and between heavily doped source/drain regions
18
and channel region
19
, to define graded junction regions
33
. The lightly doped diffusion regions are frequently formed prior to provision of sidewalls
32
.
A problem can occur in utilizing the field effect transistor structure
12
of
FIG. 1
in DRAM devices. DRAM devices normally operate with a wordline voltage in excess of power supply voltage (a so-called boosted wordline). Accordingly, transistor gates utilized in gated DRAM structures are exposed to larger electric fields than in other devices, and are more subject to breakdown and failure. Also, DRAM retention time depends on the storage node junction leakage, which in turn can be affected by the electric field at intersecting corners of the gate and the drain junction. The electric field between the gate and the drain junction often induces more junction leakage and is frequently referred to as Gate Induced Drain Leakage (GIDL). It is therefore desirable to have a thickened gate oxide region at the corner of the gate and the drain to reduce the electric field, and hence the leakage.
One of the techniques utilized to enhance integrity of transistor gates is to oxidize a portion of a semiconductive material substrate proximate the gate to form small “bird's beak” structures beneath sidewall edges
30
. Such technique is illustrated in
FIG. 2
wherein wafer fragment
10
is illustrated at a processing step subsequent to the formation of gate structure
16
, but prior to formation of spacers
32
and source/drain regions
18
. An upper surface of semiconductive material wafer
14
has been oxidized to form a silicon dioxide layer
34
which connects with gate oxide
20
. Silicon dioxide layer
34
comprises small bird's beak regions
36
which extend beneath sidewalls
30
. Silicon dioxide layer
34
also extends along a portion of sidewall
30
corresponding to the sidewall edges of semiconductive-material layer
22
, as such edges are oxidized during the oxidation of the upper surface of semiconductive material
14
.
A problem which occurs with the processing of
FIG. 2
is that sidewall edges of metal layer
26
can be oxidized during the oxidation of semiconductive material
14
. Oxidation of metal layer
26
forms metal oxide regions
38
. The volume expansion associated with the formation of metal oxide regions
38
can cause lifting of the metal lines, which can result in failure of field effect transistor structures incorporating gate structure
16
.
Among the techniques which have been utilized to avoid oxidation of the metal edge are wet hydrogen oxidation, and the utilization of silicon nitride or silicon dioxide to protect the edges. Additionally, silicon oxynitride has been utilized to cover edges of the metal material in the gate stack prior to oxidation of an upper surface of semiconductive material
14
.
The above-described problems are not limited to field effect transistor technologies. The problems can also occur in stacks utilized for other memory devices, such as, for example, the gate stacks utilized in flash memory devices.
FIG. 3
illustrates a semiconductor wafer fragment
50
comprising a semiconductive material substrate
52
, and a flash memory device gate stack
54
formed over substrate
52
. Substrate
52
can comprise, for example, monocrystalline silicon lightly doped with a p-type background dopant. Gate stack
54
comprises a gate oxide layer
56
(which can comprise silicon dioxide), a floating gate
58
(which comprises semiconductive material, which can comprise Si and Ge, and which typically comprises conductively doped polysilicon), an intergate dielectric layer
60
(which can comprise silicon dioxide), a conductively-doped-semiconductive-material layer
62
(which can comprise conductively doped polysilicon), a barrier layer
64
(which can comprise a metal nitride), a metal layer
66
(which can comprise tungsten, titanium or molybdenum), and an insulative cap
68
(which can comprise silicon nitride).
FIG. 3
also shows an oxide layer
69
over substrate
52
, and Lightly Doped Diffusion (LDD) regions
71
implanted beneath oxide layer
69
and proximate gate stack
54
. LDD regions
71
can be formed by, for is example, implanting n-type conductivity enhancing dopant (such as phospho

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