Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-21
2003-03-18
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S272000, C438S589000
Reexamination Certificate
active
06534366
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to power MOSFETs and in particular to a power MOSFET which has a greater cell packing density and therefore a lower on-resistance but without sacrificing the ability of the MOSFET to resist punchthrough breakdown.
BACKGROUND OF THE INVENTION
The design of a power MOSFET entails a number of objectives, many of which are in conflict. Several important objectives are: to minimize the resistance of the device when it is turned on, frequently referred to as the “on-resistance”; with trench-gated MOSFETs, to protect the corners of the trench against high electric fields that can generate hot carriers and damage the gate oxide layer; to minimize the threshold voltage necessary to turn the MOSFET on; and to maximize the resistance of the device to punchthrough breakdown across its channel region.
U.S. Pat. No. 5,072,266 to Bulucea et al. teaches the formation of a deep body diffusion in the center of the MOSFET cell to protect the corners of the trench against high electric fields and hot carrier generation. An example of such a MOSFET is shown in
FIG. 1
, which shows a trench-gated MOSFET
10
including a gate
11
, an N+ source region
12
, a P-body
13
, and a drain
14
which includes an N+ substrate
15
and an N-epitaxial layer
16
. N+ source region is contacted by a metal layer
17
and drain
14
is contacted by a metal layer
18
. In accordance with the teachings of the Bulucea et al. patent, a deep P+ diffusion
19
is formed in the center of the MOSFET cell. Deep P+ diffusion
19
is formed by implanting P-type dopant through the surface of the epitaxial layer
16
and heating the device to cause the dopant to diffuse downward to a level below the floor of the gate trench. The presence of the deep P+ diffusion causes the device to break down in the bulk silicon at the center of the MOSFET cell.
While the deep P+ diffusion does help to prevent hot carrier generation near the gate, it tends to limit the width W of the MOSFET cell and therefore the number of cells that can be formed within a given area of the chip. This in turn limits the on-resistance of the device, because the total cell perimeter available to conduct current generally increases with the cell density. Conversely, if W is made too small, an excessive amount of P-type dopant gets into the channel region
13
A during the diffusion process, and this increases the threshold voltage of the device.
Accordingly, there is a need for a power MOSFET which is not vulnerable to hot carrier injection and yet allows a greater packing density so as to reduce its on-resistance.
SUMMARY OF THE INVENTION
A power MOSFET in accordance with this invention includes a semiconductor substrate of a first conductivity type and an epitaxial layer formed on a surface of the substrate, the epitaxial layer including a portion in contact with the substrate. The doping concentration of the portion of the epitaxial layer is lighter than the doping concentration of the substrate. A trench is formed at a surface of the epitaxial layer, the trench extending into the epitaxial layer and having a plurality of sections which define a MOSFET cell. A gate is formed in the trench.
A source region of the first conductivity type is located adjacent a sidewall of the trench at a surface of the epitaxial layer in the MOSFET cell. A body of a second conductivity type adjoins the source region in the MOSFET cell, the body comprising a channel region adjacent the sidewall of the trench. A drain of the first conductivity type forms a first PN junction with the body, the body being located above the first PN junction, the drain being located below the first PN junction. The entire first PN junction is located at a level above a bottom of the trench, a portion of the first PN junction near the sidewall of the trench having a first breakdown voltage.
A heavily-doped region of the second conductivity type is formed within the body at a central region of the MOSFET cell, the dopant concentration of the heavily-doped region being greater than the doping concentration of the body, such that a diode comprising a portion of a second PN junction at the central region of the MOSFET has a second breakdown voltage, the second breakdown voltage being lower than the first breakdown voltage. As a result, avalanche breakdown takes place at the central region of the MOSFET cell rather than near the sidewall of the trench where hot carriers could cause damage to the gate oxide layer. The lower boundary of the heavily-doped region preferably extends to a level that is below the bottom junction of the body region but above the bottom of the trench.
Another aspect of the invention includes a method of fabricating a power MOSFET. The method comprises providing a semiconductor substrate of a first conductivity type; growing an epitaxial layer of the first conductivity on a surface of the substrate; forming a trench in the epitaxial layer, the trench defining a cell of the MOSFET; forming a first insulating layer on a surface of the trench; forming a gate in the trench, the gate being separated from the epitaxial layer by the insulating layer; implanting dopant of a second conductivity type into the epitaxial layer to form a body, a lower boundary of the body forming a first PN junction with a portion of the epitaxial layer of the first conductivity type; implanting dopant of the first conductivity type into the epitaxial layer to form a source region; depositing a second insulating layer over the epitaxial layer; forming an opening in the second insulating layer to expose at least a portion of the source region; implanting additional dopant of the second conductivity type into the epitaxial layer to form a heavily doped region, the heavily doped region being spaced apart from a wall of the trench and forming a second PN junction with the portion of the epitaxial layer of the first conductivity type; depositing a metal layer over the second insulating layer such that the metal layer contacts the portion of the source region; and limiting the thermal energy to which the power MOSFET is exposed following the implantation of the body such that the body does not diffuse substantially. As a result, the body remains quite compact and a high cell packing density can be obtained.
In one embodiment, the thermal budget following the formation of the first insulating layer through the deposition of the metal layer is less than or equal to the equivalent of 950° C. for 60 minutes. In another embodiment, the thermal budget following the formation of the first insulating layer through the deposition of the metal layer is less than or equal to the equivalent of 900° C. for 50 minutes.
REFERENCES:
patent: 6049108 (2000-04-01), Williams et al.
patent: 6285060 (2001-09-01), Korec et al.
patent: 0 583 028 (1994-02-01), None
Frank Goodenough, “Trench Technology Maximizes Power MOSFET Efficiency for Laptops”, Electronic Design, Jan. 26, 1998, pp. 41, 43 and 44.
Darwish Mohamed N.
Korec Jacek
Pitzer Dorman C.
Picardat Kevin M.
Siliconix incorporated
Skjerven Morrill LLP
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