Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-03
2003-04-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S597000, C438S738000, C438S618000, C438S637000, C438S638000, C438S689000, C438S695000
Reexamination Certificate
active
06551915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to damascene methods for forming conductor structures within microelectronic fabrications. More particularly, the present invention relates to damascene methods for forming structurally stable low contact resistance conductor structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor structures which are separated by microelectronic dielectric structures.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor structure dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ when fabricating microelectronic fabrications patterned microelectronic conductor structures formed of copper containing conductor materials, which in turn are separated by microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials (i.e., dielectric materials having a dielectric constant of less than about 4.0, in comparison with more conventional dielectric materials having a dielectric constant of greater than about 4.0). Similarly, the foregoing microelectronic conductor structures and microelectronic dielectric structures are generally formed within microelectronic fabrications while employing damascene methods, and in particular dual damascene methods.
Patterned microelectronic conductor structures formed of copper containing conductor materials are desirable in the art of microelectronic fabrication insofar as copper containing conductor materials are generally recognized as providing superior electrical conductivity in comparison with other conductor materials which may be employed for forming microelectronic conductor structures within microelectronic fabrications, such as but not limited to aluminum containing conductor materials which may alternatively be employed for forming microelectronic conductor structures within microelectronic fabrications.
In addition, microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication insofar as comparatively low dielectric constant dielectric materials typically provide microelectronic fabrications with enhanced microelectronic fabrication speed, attenuated patterned microelectronic conductor structure parasitic capacitance and attenuated patterned microelectronic conductor structure cross-talk.
Finally, damascene methods are desirable within the art of microelectronic fabrication for forming patterned microelectronic conductor structures separated by microelectronic dielectric structures within microelectronic fabrications insofar as damascene methods may often be employed to form patterned microelectronic conductor structures separated by microelectronic dielectric structure within microelectronic fabrications with fewer process steps, such as to provide patterned microelectronic conductor structures separated by microelectronic dielectric structures which may not otherwise be readily formed within microelectronic fabrications.
While microelectronic fabrications formed of patterned microelectronic conductor structures formed of copper containing conductor materials separated by microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials, as formed employing damascene methods, are thus desirable in the art of microelectronic fabrication, such microelectronic fabrications formed of microelectronic conductor structures formed of copper containing conductor materials separated by microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is known in the art of microelectronic fabrication that microelectronic fabrications formed of microelectronic conductor structures formed of copper containing conductor materials separated by microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials, as formed employing damascene methods, are often difficult to fabricate with decreased contact resistance and with enhanced structural integrity, in particular of the microelectronic conductor structures.
It is thus desirable in the art of microelectronic fabrication to fabricate microelectronic fabrications having formed therein patterned microelectronic conductor structures formed of copper containing conductor materials separated by microelectronic dielectric structures formed of comparatively low dielectric constant dielectric materials, while employing damascene methods, to provide the microelectronic fabrications with decreased contact resistance and enhanced structural integrity.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for fabricating, with desirable properties, microelectronic fabrications within the art of microelectronic fabrication.
Included among the methods, but not limiting among the methods, are methods disclosed by: (1) Wu et al., in U.S. Pat. No. 6,071,806 (a dual damascene method for forming, with decreased contact resistance within a microelectronic fabrication, a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via defined within a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material by first exposing the sidewalls and floor of the trench contiguous with the via to an electron beam treatment prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer); and (2) Ellingboe et al., in U.S. Pat. No. 6,114,250 (a plasma etch method for forming within a microelectronic fabrication a patterned dielectric layer of a comparatively low dielectric constant dielectric material, where the patterned dielectric layer of the comparatively low dielectric constant dielectric material may be employed for forming a dual damascene structure within the microelectronic fabrication, and where the plasma etch method employs an etchant gas composition comprising hydrogen and nitrogen).
Desirable in the art of microelectronic fabrication are additional damascene methods for forming within microelectronic fabrications patterned microelectronic conductor structures separated by microelectronic dielectric structures, with decreased contact resistance and enhanced structural integrity.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned conductor layer.
A second object of the present invention is to provide the damascene method in accord with the first object of the present invention, wherein the patterned conductor layer is formed with decreased contact resistance and increased structural integrity.
A third object of the present invention is to provide the damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a damascene method for forming a patterned conductor layer within a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a blanket first dielectric layer. There is then patterned the blanket first dielectric layer to form a patterned first dielectric layer which defines an aperture. Finally, there is then formed into the aperture a patterned co
Lin Jing-Cheng
Shue Shau-Lin
Smith Matthew
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
Yevsikov V.
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