Method for removing etching residues

Details Method for removing etching residues Method for removing etching residues

2001-02-21

2003-04-29

Goudreau, George (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001300, C438S725000, C438S714000, C438S704000, C438S734000, C438S740000, C438S744000, C438S757000, C438S750000

Reexamination Certificate

active

06554002

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for removing etching residues, and relates more particularly to a method for removing fluorine-containing etching residues that can result in poor adhesion between the barrier layer and the low-k dielectric layer.
2. Description of the Prior Art
Many highly integrated semiconductor circuits utilize multilevel wiring line structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. In forming a second level wiring line in contact with the first level wiring lines or interconnect structures, a first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. Alternately, a first level interconnect might be formed to a polysilicon or metal wiring line that is in contact with one or more device structures in or on the substrate of the integrated circuit device. One or more interconnects are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished, in part, through the second level of wiring lines.
The utility of copper material and low dielectric constant material are been developing in some new manufacturing processes for finding a resolution to the RC delay problem resulting from the decrease of devices size. One alternative to the conventional interconnect formation process is the so-called dual damascene process. Dual damascene processes are more immediately scaleable to smaller design rules and most dual damascene processes naturally produce a planarized final surface over the interconnect structure. Accordingly, a surface that is appropriate for further process steps can be obtained using the dual damascene process in fewer process is illustrated in FIG.
1
.
FIG. 1
is a cross-sectional diagram illustrating a Cu/low-k dual damascene structure. A copper conductor structure
130
is adjacent to a first low-k dielectric layer
110
and a cap layer
140
is formed thereon. An etched second low-k dielectric layer
120
with a pattern is on the cap layer
140
.
Next, the exposed cap layer
140
is etched. However, the etching step is implemented by fluorine-contained plasmas, such as CH
2
F
2
—O
2
—Ar plasma, and some fluorinated polymeric material is formed nearby during the etching process. Then the etching residues are removed during the post-etch cleaning process. In general, the etching residues are removed by use of a conventional amine-based inorganic solvent, such as APM cleaning (NH
4
OH/H
2
O
2
/H
2
O). However, it is difficult to remove the fluorinated polymeric material by such an amine-based inorganic solvent. The residual fluorinated polymeric material may result in poor adhesion between low-k dielectric layer and barrier metals in subsequent steps, and may further result in peeling problems. Accordingly, the fluorinated polymeric material needs to be absolutely removed during post-etch cleaning.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for completely removing polymeric material residues during post-etch cleaning. The addition of sputtering step in post-etch cleaning process can destroy the structure of the polymeric material residues.
It is another object of the present invention to provide a method for preventing poor adhesion of the barrier layer in via and trench devices. An etching residue is removed by the addition of a baking process in the post-etch cleaning process.
In the present invention, a method for removing fluorine-containing etching residues during dual damascene process comprises providing a damascene structure having a copper conductor structure therein, a cap layer formed on the copper conductor structure and the damascene structure, and a low dielectric constant dielectric layer on the cap layer. The low dielectric constant dielectric layer formed by spin-on polymer method has at least an opening above the copper conductor structure. The cap layer is etched by fluorine-containing plasma to expose the copper conductor structure. The damascene structure is cleaned with a solvent and then the fluorine-containing etching residues are removed by plasma sputtering treatment or baking, or combination of both. The addition of baking and plasma sputtering treatment can prevent poor adhesion between coming metal diffusion barrier layer and the low dielectric constant dielectric layer.


REFERENCES:
patent: 6177347 (2001-01-01), Liu et al.
patent: 6323121 (2001-11-01), Liu et al.
patent: 6380096 (2002-04-01), Hung et al.
patent: 6417114 (2002-07-01), Peyne et al.

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