Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-19
2003-05-06
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S329000, C257S336000
Reexamination Certificate
active
06559011
ABSTRACT:
FIELD OF THE INVENTION
The field of this invention is design and fabrication of double diffused MOS (DMOS) transistors.
BACKGROUND OF THE INVENTION
DMOS transistors are used widely in both RF analog and mixed-signal integrated circuits (ICs), and in dielectrically isolated ICs for power and high voltage applications. In many of these applications hot carrier injection is a recognized problem. Prior efforts to minimize hot carrier injection include increasing the gate dielectric thickness, increasing the channel length, and reducing the drain doping concentration. However, all of these options carry drawbacks, and are inconsistent with state of the art goals of shrinking technology dimensions. Thicker gate dielectrics reduce the transconductance and power gain and frequency performance. Increasing channel length also results in reducing the transconductance and power gain. Reducing the drain doping level increases drain resistance and reduces output power.
There remains a need for better techniques to reduce hot carrier effects in MOS transistors, as technology dimensions shrink for better device performance.
STATEMENT OF THE INVENTION
I have developed an improved MOS device design and fabrication method that addresses hot carrier problems and other adverse edge effects of MOS transistor gates by using a dual level gate. The dual level gate is realized according to the process aspect of the invention by forming a standard MOS polysilicon gate structure, forming the source and drain regions, then with the source and drain windows open, wet etching (or its equivalent) the gate dielectric using the polysilicon gate as a mask. This results in a substantial undercut of the edges of the polysilicon gate. The gate structure is then thermally oxidized to grow oxide in the undercut regions. The thermal oxidation is allowed to proceed until the oxide thickness at the edge exceeds the oxide thickness in the center region of the gate structure. This results in uniform lifting of the gate at the gate edges. The effective gate dielectric thickness in the regions of the gate that control hot carrier and other edge effects is thereby selectively increased.
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Lebentritt Michael S.
Thomas Kayden Horstemeyer & Risley LLP
Wilde Peter V. D.
Wilson Christian D.
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