Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-03
2003-07-22
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S262000, C438S266000, C438S786000, C257S314000, C257S318000, C257S321000
Reexamination Certificate
active
06596587
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to electrically-erasable-programmable-read-only-memory (EEPROM) devices and, more particularly, to EEPROM devices and methods for fabricating EEPROM devices having shallow junctions, while maintaining high capacitive coupling.
BACKGROUND
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the (electrically-erasable-programmable-read-only-memory) EEPROM device. In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode may be formed in a region of the substrate referred to in the art as a control gate region. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
Single poly EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two transistor design or a three transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a sense transistor. In a two transistor device, the functions of read and sense transistors are combined into a single transistor. To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low voltage Vpp is applied to the drain (bitline contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bitline to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition-that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bitline and a high voltage Vpp+ is applied to the control-gate. Under this bias condition, the high voltage applied to control-gate is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode. The efficient application of high voltage to the write transistor and the sense transistor during program and erase cycles requires that the gate dielectric layers of these transistors have a similar thickness to the dielectric layer separating the program junction regions (which comprise a tunnel region and a control-gate region) from the overlying floating-gate electrode.
As PLD EEPROM devices are scaled to smaller dimensions, the junction depth of the program junction regions must be reduced. As used herein, the term “program junction region” refers to a highly doped junction region in the substrate underlying the tunnel region and the control-gate region. The program junction region is also known by various terms, such as the tunneling implant region. The most straightforward way to reduce the junction depth of the program junction regions is to simply reduce their doping concentrations. Reducing the doping concentration in the control-gate region, however, increases the depletion level during operation of the device. Large depletion levels, in turn, reduce the desired capacitive coupling to the floating-gate electrode.
The reduction in capacitive coupling can be compensated for by increasing the capacitor area, but this can result in a larger EEPROM memory cell. Thus, maintaining a controlled amount of depletion in the control-gate region, while avoiding increasing the capacitor area, requires that the doping level in the control-gate region be kept at a high level. A large doping concentration, however, functions to undesirably increase the thickness of the capacitor dielectric layer during thermal oxidation processes used for device fabrication. A localized variation in dielectric thickness leads to a discrepancy in dielectric thickness between the tunnel region and capacitor region, and also between the write and sense transistors and the capacitor dielectric. Accordingly, a need exists for an EEPROM device fabrication process that enables the fabrication of shallow junction devices, while maintaining uniform dielectric layer thickness, and that does not require a corresponding increase in capacitor area.
SUMMARY
The present invention provides an EEPROM device and a process for fabricating an EEPROM device having shallow junctions. The process enables the control-gate region of an EEPROM device to have a higher doping concentration than the tunnel region, while providing for a uniform dielectric layer thickness over both the tunnel region and the control-gate region. Further, the process of the invention enables the fabrication of a sufficiently highly doped control-gate region, such that a high capacitance coupling is obtained between the control-gate region and the floating-gate electrode.
In one aspect, the process of the invention includes forming a control-gate region and a tunnel region and a semiconductor substrate. The tunnel region is characterized by a first doping concentration. The doping concentration in the control-gate region is selectively increased to a concentration greater than the first doping concentration in the tunnel region. Then, nitrogen is introduced into the control-gate region and a dielectric layer is thermally formed to overlie the control-gate region and the tunnel region. In accordance with the process of the invention, the dielectric layer has substantially the same thickness over both the control-gate region and the tunnel region. A floating-gate electrode is then formed to overlie the control-gate region and the tunnel region and is separated from the control-gate region and the tunnel region by the dielectric layer.
In another aspect, the invention includes an EEPROM device having a control-gate region and a tunnel region formed in a semiconductor substrate. The tunnel region has a first doping concentration and the control-gate region has a second doping concentration that is greater than the first doping concentration. A dielectric layer of substantially the same thickness overlies both the control-gate region and the tunnel region, and a floating-gate electrode overlies the control-gate region and the tunnel region and is separated from the control-gate region and the tunnel region by the dielectric layer. The control-gate region includes sufficient nitrogen to inhibit the growth of the dielectric layer overlying the control-gate region, such that the dielectric layer has a substantially uniform thickness over both the control-gate region and the tunnel region.
REFERENCES:
patent: 5132239 (1992-07-01), Ghezzi et al.
patent: 5672521 (1997-09-01), Barsan et al.
patent: 5942780 (1999-08-01), Barsan et al.
patent: 6255169 (2001-07-01), Li et al.
Lattice Semiconductor Corporation
Vockrodt Jeff
Zarabian Amir
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