Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-02-22
2003-04-22
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S067000, C216S079000, C438S719000, C438S723000, C438S734000, C438S739000, C438S743000
Reexamination Certificate
active
06551941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of forming a notched silicon-containing gate structure. In particular, the present invention provides a multiple step method of forming a notched silicon-containing gate structure which provides good control over notch dimensions and excellent notch dimension uniformity across the surface of a substrate.
2. Brief Description of the Background Art
Integrated circuit (IC) technology has advanced from large scale integration (LSI) to very large scale integration (VLSI). Over the next several years, IC technology is projected to grow to ultra-large scale integration (ULSI). The advancement in monolithic circuit integration has been made possible by improvements in semiconductor manufacturing equipment, as well as in the materials and methods used in processing semiconductor wafers into IC chips.
As integrated circuit technology advances, the requirements of the basic integrated circuit fabrication steps of masking, film formation, doping, and etching are becoming increasingly more stringent. Important factors affecting IC fabrication are the use of greater device densities and smaller minimum feature sizes with smaller separations. Other factors include the use of composite conductive layers, such as silicides, and the increasing importance of the third wafer dimension, where dimensions and shapes must be maintained on vertical surfaces, such as in notches for polysilicon gates. These requirements must be met for a wide range of feature sizes and densities, with no sacrifice of precision.
Polysilicon gates with a substantially square cross-section are often used to form the control electrode for a device. This shape minimizes the resistance of the gate as a function of gate spacing. The resistance of a polysilicon gate, combined with the capacitance of the gate, forms a low-pass filter, which inhibits the speed of the device.
Gate width is a very important factor in integrated circuit manufacture, since it defines the length of the integrated circuit device. Since the ability to accurately define small geometries with existing lithography is limited, the polysilicon gate must often be made wider than desired. The gate can be etched for an additional period of time, but the result has often been a compromise involving limits imposed by photolithographic capability, resistance, and polysilicon gate width.
As discussed above, the ability to etch narrow, high aspect ratio polysilicon gates is important in the formation of integrated circuits. Various methods of forming polysilicon gate structures are provided, for example, in U.S. Pat. No. 4,577,392, to Peterson; U.S. Pat. No. 5,808,340, to Wolleson et al.; U.S. Pat. No. 5,844,836, to Kepler et al.; U.S. Pat. No. 5,960,271, to Wolleson et al.; U.S. Pat. No. 6,004,007, to Capodieci; U.S. Pat. No. 6,107,667, to An et al.; and U.S. Pat. No. 6,136,674, to An et al.
T-shaped polysilicon gate structures, where the top portion of the gate is wider than the bottom portion of the gate, have come into use in recent years. Because a T-shaped gate is wider at the top, it is easier to define, allowing standard photolithography techniques to be used. Further, the wider top of the T-shaped gate structure provides a greater contact area, which allows overlying devices to be more easily aligned to the gate when preparing a multi-layered structure, while the narrower gate length at the bottom of the gate structure provides decreased gate resistance. T-shaped polysilicon gate structures are discussed, for example, by T. Ghani et al. in a publication entitled “100 nm Gate Length High Performance/Low Power CMOS Transistor Structure” (1999 IEEE).
In order to form a T-shaped gate structure, it is necessary to form a notch at the bottom of a polysilicon gate structure which has a substantially square cross-section. The notch is typically formed at the interface of the polysilicon gate and an underlying gate dielectric layer. Prior art processes for forming notched polysilicon gate structures have suffered from inconsistent etch profiles. For example, when conventional processing methods are used, the sides of a polysilicon gate may either slope outward at the bottom, be substantially vertical, or be only minimally notched.
In addition, during etching of notches in a polysilicon gate structure, it is important to be able to maintain good control over both vertical and lateral etching in order to obtain notches having the etch profile and critical dimensions needed for the final device requirements. It is equally important that the notch etching process occurs evenly across the surface of the substrate (typically, a silicon wafer). It would therefore be desirable to provide a method of forming a notch in a polysilicon gate structure which provides good critical dimension control during etching and critical dimension uniformity across the entire substrate.
SUMMARY OF THE INVENTION
We have developed a multiple step method of forming a notched silicon-containing gate structure. The method of the invention provides control over notch dimensions (height vs. width) and excellent etch uniformity across the substrate surface.
The method of the invention for forming a notched silicon-containing gate structure comprises the following steps:
a) providing an etch stack including, from top to bottom, a patterned masking layer, a silicon-containing gate layer, a gate dielectric layer, and an underlying substrate;
b) etching the silicon-containing gate layer to a first desired depth using a plasma generated from a first source gas, to form a first passivation layer on sidewalls of the silicon-containing gate layer which are exposed during etching, whereby upper silicon-containing gate layer sidewalls are protected from etching during subsequent etching steps;
c) etching the remaining portion of the silicon-containing gate layer using a plasma generated from a second source gas which selectively etches the silicon-containing gate layer relative to the gate dielectric layer, to form a lower sidewall of the silicon-containing gate layer and to expose an upper surface of the gate dielectric layer;
d) exposing the etch stack to a plasma generated from a third source gas which includes nitrogen, to form a second, nitrogen-containing passivation layer on the exposed sidewalls of the etched silicon-containing gate layer; and
e) etching a notch in the lower sidewall of the silicon-containing gate layer which is not protected by the first passivation layer, using a plasma generated from a fourth source gas which selectively etches the silicon-containing gate layer relative to the gate dielectric layer.
In addition to protecting the upper sidewalls of the silicon-containing gate layer from etching during subsequent processing steps, the first passivation layer substantially defines the height of the notch which is etched in step (e).
We have found that exposing the etched silicon-containing gate layer to a plasma containing nitrogen, prior to etching notches in the lower sidewall of the etched silicon-containing gate layer, results in the preferential deposition of nitrogen-containing passivation layers on sidewalls in isolated areas of the substrate. This counteracts the inherent tendency toward more rapid notch etching in isolated areas of the substrate. The result is that isolated and dense areas of the substrate tend to etch at equal rates, providing excellent etch uniformity and critical dimension uniformity across the surface of the substrate.
Also disclosed herein is a method of controlling a line width at the base of a silicon-containing gate structure. This method comprises the following steps:
a) providing an etch stack including, from top to bottom, a patterned masking layer, a silicon-containing gate layer, a gate dielectric layer, and an underlying substrate;
b) etching the silicon-containing gate layer to a first desired depth using a plasma generated from a first source gas, to form a first passivation layer on sidewalls of the silicon-containing gate layer which are exposed
Chinn Jeffrey D.
Shen Meihua
Yang Chan-syun David
Yauw Oranna
Applied Materials Inc.
Bach Joseph
Bean Kathi
Church Shirley L.
Powell William A.
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