Methods for fabricating semiconductor devices

Details Methods for fabricating semiconductor devices Methods for fabricating semiconductor devices

1999-11-11

2003-03-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S636000, C438S585000, C438S778000

Reexamination Certificate

active

06537906

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for their manufacture, and more particularly, certain embodiments relate to etching a conductive layer containing silicon.
BACKGROUND
In the fabrication of a semiconductor device, for example, a gate electrode is formed by partially etching a conductive layer such as a polysilicon layer formed on a semiconductor substrate with an insulating film therebetween. Such etching is performed using a predetermined resist pattern, formed by photolithography, as a mask, in order to obtain predetermined shape and size. Therefore, it is an important technique to obtain a predetermined photo-pattern for forming gate electrodes. In accordance with the recent reduction in size of gate electrode structures, the following phenomenon has been occurring at a step in the end of a device-separation region. The phenomenon will be described with reference to
FIGS. 8 and 9
.
FIG. 8
is a sectional view of a device when a gate electrode is formed in the vicinity of a device-separation region. A first step
130
a
lies in the end of a device-separation region
112
formed on a silicon substrate
110
on the side of a gate oxide film
124
. When a polysilicon layer
126
is deposited on the device-separation region
112
and the gate oxide film
124
, a second step
130
b
is also generated in the polysilicon layer
126
lying above the first step
130
a.
With the second step
130
b
being present, for example, the following problem may occur.
In order to etch the polysilicon layer
126
in a predetermined shape, dry etching or the like is generally performed using a pattern formed with a resist as a mask. Resist patterning is performed by exposure and development of the resist. Consequently, in a resist layer R
1
shown in
FIG. 8
, in order to remove a resist layer portion R
1
a
in the region between chained lines A and B, the resist layer portion R
1
a
only must be exposed if a positive resist is used. When the resist layer portion R
1
a
between the chained lines A and B is exposed, the exposure light passes through the resist layer portion R
1
a
and is reflected by the interface between the resist layer R
1
and the polysilicon layer
126
. Therefore, light reflected by the section having a horizontal surface of the polysilicon layer
126
, such as a first exposure light
140
a,
is reflected in the opposite direction to the incident light. On the other hand, light reflected by the second step
130
b,
such as a second exposure light
140
b,
is reflected in various directions depending on the tilt angle of the second step
130
b,
and the reflected light may penetrate through a resist layer R
1
b
which is required to remain, thus exposing the resist layer R
1
b.
When the above is developed, as shown in
FIG. 9
, the end of the remaining resist layer R
1
b
is missing and satisfactory patterning of the resist layer is not obtained.
In order to solve such a problem, Japanese Unexamined Patent Publication No. 8-153704 discloses a technique in which an organic antireflection coating is disposed between the polysilicon layer
126
and the resist layer R
1
. By providing such an organic antireflection coating, the organic antireflection coating absorbs the exposure light passing through the resist layer and prevents the exposure light from being reflected at the interface between the resist layer and the organic antireflection coating, and thus a resist mask having predetermined size and shape can be obtained.
However, the organic antireflection coating is not removed when the resist mask is formed, and remains on the polysilicon layer. Therefore, in order to etch the polysilicon layer using the resist mask, the organic antireflection coating must be etched in predetermined size and shape using the resist mask.
Consequently, in the fabrication of a gate electrode using an organic antireflection coating as well as using a resist mask formed by photolithography, two processes of etching are used, namely, etching of the organic antireflection coating in which size and shape are controlled using the resist mask; and etching of the gate electrode in which size and shape are controlled using a mask including the resist and the organic antireflection coating.
SUMMARY
One embodiment relates to a method for fabricating a semiconductor device including forming an insulating film on a semiconductor substrate and forming a conductive layer containing silicon on the insulating film. A stopper layer is formed on the conductive layer and an organic antireflection coating formed on the stopper layer. A resist layer having a predetermined pattern is formed on the organic antireflection coating. The method also includes etching the organic antireflection coating using the resist layer as a mask, as well as etching the stopper layer and etching the conductive layer in a predetermined pattern to form a gate electrode.
Certain other embodiments relate to method for fabricating a semiconductor device including forming an insulating film on a semiconductor substrate and forming a conductive layer on the insulating film. A stopper layer is formed on the conductive layer and an antireflection coating is formed on the stopper layer. A resist layer having a predetermined pattern is formed on the antireflection coating. The method also includes etching the antireflection coating using the resist layer as a mask, as well as etching the stopper layer and etching the conductive layer in a predetermined pattern.
Additional embodiments relate to a method for fabricating a semiconductor device including forming an insulating film on a semiconductor substrate and forming a conductive layer containing silicon on the insulating film. A stopper layer is formed on the conductive layer and an organic antireflection coating formed on the stopper layer. The organic antireflection coating is etched and the stopper layer is etched. In addition, the conductive layer is etched in a predetermined pattern.
Embodiments also relate a gate electrode including an insulating film on a substrate and a conducting layer on the insulating film. The gate electrode also includes a stopper layer on the conducting layer, the stopper layer being a material having a lower etching rate than an organic antireflection material when subjected to an etching gas comprising oxygen and chlorine.


REFERENCES:
patent: 5017513 (1991-05-01), Takeuchi
patent: 5728508 (1998-03-01), Takemura et al.
patent: 5920796 (1999-07-01), Wang et al.
patent: 6004722 (1999-12-01), Zhang
patent: 6004853 (1999-12-01), Yang et al.
patent: 6046114 (2000-04-01), Tohda
patent: 6136676 (2000-10-01), Saito
patent: 0605123 (1994-07-01), None
patent: 0820093 (1998-01-01), None
patent: 5-304167 (1993-11-01), None
patent: 6-020943 (1994-01-01), None
patent: 7-335869 (1995-12-01), None
patent: 8-153704 (1998-06-01), None
patent: 10-242117 (1998-09-01), None
patent: 10-303183 (1998-11-01), None
patent: 10-341104 (1998-11-01), None
patent: 2000-31018 (2000-01-01), None
patent: 200031018 (2000-01-01), None
U.S. application Ser. No. 09/438,164, filed Nov. 11, 1999.
Translation of “Notice of Grounds for Rejection” re: Japanese 1999 Patent Application 251217, date of notice Apr. 4, 2001.
Ta et al., “A sub-micron deep-UV integrated ARC process”, Proc. Electrochem. Soc. (1992) 92-18, pp. 460-471.

Affiliated with

Also associated with

Rating

Methods for fabricating semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for fabricating semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3003823