Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-29
2003-01-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S353000
Reexamination Certificate
active
06503802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, and more particularly, to a method of fabricating an isolation structure for a semiconductor device.
2. Description of the Background Art
Isolation structures are used in semiconductor devices to isolate electrically different components of the semiconductor devices. Once the components are isolated from each other, certain electrical paths can be established between the components to obtain desired electrical characteristics from the semiconductor device.
Conventional methods for fabricating an isolation structure for a semiconductor device typically employ a LOCal Oxidation of Silicon (LOCOS) process. In the LOCOS process, a field oxide is thermally grown by using an oxidation mask to pattern the growth. However, a portion of the field oxide grows laterally, thereby producing tapering oxide wedge portions outside the desired growth pattern. These oxide wedge portions are referred to as a “bird's beak” due to the shape of the wedge portions. The bird's beak reduces the isolation area between the components of the semiconductor device and can deteriorate the electrical performance of the semiconductor device.
To overcome this problem, a shallow trench isolation (STI) structure or profiled groove isolation (PGI) structure has been developed as an isolation structure. In the STI or PGI, a trench or groove is formed in a semiconductor substrate and filled with insulating materials to provide the isolation feature. Most of conventional Dynamic Random Access Memory (DRAM) devices are fabricated by employing such an STI or PGI structure.
A conventional method of fabricating an STI structure is described below with reference to
FIGS. 1A through 1F
. First, as illustrated in
FIG. 1A
, a pad oxide film
101
and a nitride film
102
are sequentially formed on the top surface of a semiconductor substrate
100
. Then, as illustrated in
FIG. 1B
, a photoresist pattern
103
is formed on the top surface of the nitride film
102
. Then the nitride film
102
and the pad oxide film
101
are sequentially etched by using the photoresist pattern
103
as a mask to expose a certain portion of the top surface of the semiconductor substrate
100
.
As illustrated in
FIG. 1C
, the exposed portion of the semiconductor substrate
100
is then etched to form a trench
104
in the semiconductor substrate
100
. The photoresist pattern
103
is then removed completely from the nitride film
102
and the remaining structure is cleaned. Thereafter, as illustrated in
FIG. 1D
, an oxide film
105
is formed on the exposed surface of the semiconductor substrate
100
at the inner walls and bottom surface of the trench
104
.
Next, as illustrated in
FIG. 1E
, an other oxide film
106
is formed in the trench
104
and on the exposed surfaces of the nitride film
102
. Then, as illustrated in
FIG. 1F
, the surface of the semiconductor substrate
100
is planarized by removing the entire pad oxide film
101
, the entire nitride film
102
and the portion of the oxide film
106
above the semiconductor substrate
100
. Here, a conventional chemical mechanical polishing process can be used to planarize the semiconductor substrate
100
. This produces a conventional STI structure
110
, and the fabrication method is completed.
Although effective, there is, however, a limitation associated with the STI structure
110
. The corners C of the top surface of the semiconductor substrate
100
at the entrance of the trench
104
have pointed edges. In some cases, the cleaning step and the oxide film formation step of
FIGS. 1C and 1D
may smooth these edges slightly, but the resultant corners C would still have pointed edges. The shape of the pointed edges causes electric fields to be concentrated at the corners C of the semiconductor substrate. The concentration of electric fields at the corners C causes a well-known “hump” phenomenon that degrades the electrical characteristics and performance of the semiconductor device having the STI structure
110
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an isolation structure for a semiconductor substrate which overcomes the above-described and other problems associated with conventional fabrication methods.
It is another object of the present invention to provide a method of fabricating an isolation structure for a semiconductor device in which the reliability and performance of the semiconductor device can be improved by stabilizing the electrical characteristics of the semiconductor device.
It is another object of the present invention to provide a method of fabricating an isolation structure for a semiconductor device in which the occurrence of a hump. phenomenon can be prevented by reducing significantly the sharpness at the corner of a semiconductor substrate.
To achieve the above and other objects, the present provides a method of fabricating an isolation structure for a semiconductor device, including the steps of forming a trench in a semiconductor substrate, implanting oxidation-accelerating ions into corner portions of the semiconductor substrate, forming an oxide film in the trench of the semiconductor substrate, which activates the oxidation-accelerating ions to round the corner portions of the semiconductor substrate, and filling the trench with an insulating material to fabricate the isolation structure.
The present invention is also directed to a method of fabricating an isolation structure for a semiconductor device. The method includes the steps of providing a trench in a semiconductor substrate, implanting oxidation-accelerating ions into corner portions of the semiconductor substrate, annealing the semiconductor substrate to activate the oxidation-accelerating ions, thereby rounding the corner portions of the semiconductor substrate, and filling the trench with an insulating material to fabricate the isolation structure.
The present invention is further directed to a method of fabricating an isolation structure for a semiconductor device, the method comprising the steps of: providing a trench in a semiconductor substrate; selectively accelerating oxidation speed at corner portions of the semiconductor substrate by forming an oxide film in the trench, and thereby rounding the corner portions of the semiconductor substrate; and filling the trench with an insulating material to fabricate the isolation structure.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.
REFERENCES:
patent: 6093618 (2000-07-01), Chen et al.
patent: 6156620 (2000-12-01), Punchner et al.
patent: 6333232 (2001-12-01), Kunikiyo
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Nhu David
LandOfFree
Method of fabricating isolation structure for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating isolation structure for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating isolation structure for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3001852