Mode selection circuit for semiconductor memory device

Details Mode selection circuit for semiconductor memory device Mode selection circuit for semiconductor memory device

2001-04-19

2002-10-01

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

06459636

ABSTRACT:

This application claims priority to Korean Patent Application No. 2000-37715, filed on Jul. 3, 2000, the contents of which in its entirety are herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a mode selection circuit for providing mode selection signals obtained from address data in a semiconductor memory device.
2. Description of Related Art
Semiconductor memory devices usually have test operation modes that provide various test operations to evaluate device quality as well as normal operation modes. In a semiconductor memory device, multiple mode selection signals are provided to enable various test operations. For example, the mode selection signals may be used to activate and evaluate a device according to various voltage levels of specific circuits. The mode selection signals may be used to perform test operations including normal and abnormal operations, for example, activating multiple memory banks or word lines.
FIG. 1A
shows a conventional mode selection signal generator to generate a mode selection signal in a semiconductor memory device. The mode selection signal generator includes a resistor
102
having a high resistance, a fuse
101
, and two inverters
103
and
104
. An activation or inactivation of a mode selection signal MODE is dependent upon whether the fuse
101
is cut off or not. If the fuse
101
is not cut off, a node N
1
is low level and thereby the mode selection signal MODE remains inactive. If the fuse
101
is cut off, the node N
1
is pulled-up by the resistor
102
to a high level and the mode selection signal MODE is activated.
FIG. 1B
is a block diagram of another conventional mode selection signal generator. This mode selection signal generator includes a pad
110
, diode-connected transistors
111
, a resistor
112
having high resistance, and two inverters
113
and
114
. When a high voltage is applied to the pad
110
for a mode selection, diode-connected transistors
111
are turned on, and thereby node N
2
becomes high level so that a mode selection signal MODE is activated to high level. The pad
110
is used to receive external signals in a normal operation mode. A voltage level applied to the pad
110
in the normal operation mode is not enough to enable the diode-connected transistors
111
to be turned on. Thus, the node N
2
maintains at a low level, and thereby the mode selection signal MODE remains inactive.
In the conventional mode selection circuit, however, additional operations are needed to cut off the fuse. Further, the conventional mode selection circuit has problems such as low reliability in cutting off the fuse and a relatively large layout size for the fuse. In addition, in case that a high voltage is applied to a pad which is employed in normal operation modes, the voltage level for the pad would be increased due to external factors such as noises to cause an invalid mode selection signal to be generated.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above problems and to provide a mode selection circuit ensuring a stable mode selection operation so as to prevent a memory device from being situated in an invalid operation mode.
According to one aspect of the present invention to achieve the above and other objects, the mode selection circuit includes a timing register for generating a first control signal in response to a command signal and first address data, a programming control signal generator for generating second control signals in response to second address data and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal and the second control signals. Preferably, the mode selection signals are activated in accordance with a sequential order of activation of the second control signals.
According to another aspect of the present invention, the mode selection circuit includes a timing register for generating first and second control signals in response to command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals. The mode selection signals are preferably activated in accordance with a sequential order of activation of the third control signals. The second control signal may be activated when the command signal and the first address signal have predetermined values, and the mode selection signals are reset to an inactive state in response to the second control signal.
According to the present invention, a plurality of control signals are generated which are enabled by combinations of command signal and address signals, and mode selection signals for a specific mode are activated in accordance with a sequence of activation of the plurality of control signals. Thus, more stable mode selection operation can be carried out by the mode selection signals.


REFERENCES:
patent: 5870342 (1999-02-01), Fukuda
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 6061285 (2000-05-01), Tsukikawa

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