Method of forming a dual damascene opening using CVD Low-K...

Details Method of forming a dual damascene opening using CVD Low-K... Method of forming a dual damascene opening using CVD Low-K...

2000-09-05

2002-10-29

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S723000, C438S734000, C438S738000, C438S622000, C438S633000, C438S637000, C438S638000

Reexamination Certificate

active

06472306

ABSTRACT:

BACKGROUND OF THE INVENTION
A high speed logic device with low RC delay back-end-of-line (BEOL) is preferred in present integrated circuit (IC) approaches. Copper (Cu) is chosen for its lower resistance and low dielectric constant (low-k) which minimizes capacitance in BEOL.
Dual damascene structures will be used in the next generation processes and devices. Integration of copper dual damascene structures and low-k material is the predominant trend for IC processes.
Currently, chemical vapor deposition (CVD) low-k material and spin-on-polymer (SOP) are candidates for such low-k materials. However there are many issues that need to be resolved for low-k integration in ultra large-scale integration (ULSI) processes.
SOP is likely an organic material and therefore its chemical structure is similar to photoresist material. So inorganic oxides have been used as hard masks (HM) in etching processes of SOP and the adhesion between HM and the underlying organic low-k material is very important.
U.S. Pat. No. 6,010,962 to Liu et al. describes a method for forming inlaid copper interconnects in an insulating layer without dishing after chemical-mechanical polishing of the excess copper. A lower insulating layer
110
and an upper insulating layer
130
, separated by an intervening etch stop layer
120
, are formed a substrate
100
. The upper and lower insulating layers
110
,
130
may be comprised materials formed by, for example, CVD, PECVD, PVD or low-k materials, FSG, HSQ, Flare and PAE2.
U.S. Pat. No. 6,004,883 to Yu et al. describes a method for forming a dual damascene opening and structure through a dielectric layer within a microelectronics fabrication without an etch stop layer. A lower dielectric layer consists of a first dielectric material which is not susceptible to etching within an oxygen containing plasma, such as silicon oxide, silicon nitride, and silicon oxynitride. First vias are formed within the first dielectric material. An upper dielectric layer is formed over the lower dielectric layer and consists of a second dielectric material which is susceptible to etching within an oxygen containing plasma of a ratio of at least 20:1 compared to the first dielectric material. The second dielectric material is then patterned and etched through a hard mask to form second vias coexistent with the first vias and together forming a dual damascene via opening.
U.S. Pat. No. 6,013,581 to Wu et al. describes a method for preventing poisoning of trenches and vias in a dual damascene process. A densification process, such as a plasma treatment, is performed on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densification process prevents poisoning of the trenches and vias caused by outgassing.
U.S. Pat. No. 5,817,572 to Chiang et al. describes a method for forming interconnections in semiconductor devices. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. A second patterned dielectric layer is formed over the first dielectric layer and has a second opening exposing at least a portion of the conductive material. The first dielectric layer may serve as an etch-stop layer in patterning the second dielectric layer or a separate etch-stop layer may be formed over the first dielectric layer and conductive material before formation of the second dielectric layer.
U.S. Pat. No. 6,007,733 to Jang et al. describes a method for forming a patterned layer within a microelectronics fabrication. An oxygen containing plasma etchable layer, which is also susceptible to etching within a fluorine containing plasma, is formed over a microelectronics substrate. A hard mask layer is then formed over the oxygen containing plasma etchable layer, and a patterned photoresist layer is in turn formed over the hard mask layer. The hard mask is patterned by a first anisotropic plasma etch method and the patterned photoresist layer is stripped from the patterned hard mask layer by a stripping method which does not attack the oxygen containing plasma etchable layer. A second plasma etch method is used to pattern the oxygen containing plasma etchable layer through the patterned hard mask layer. The second plasma etch method is the fluorine containing plasma etch method.
The article entitled “Pursuing the Perfect Low-k Dielectric,” Laura Peters, Semiconductor International, Sep. 1998, pp. 64-74, describes various potential low-k dielectric materials, including FSG and HSQ, to be used with copper interconnects.
The press release entitled “International Sematech Validates Manufacturing Capability of Applied Material's Low-k Solution for Copper Interconnects—Successful Results Achieved with Black Diamond for Production of Sub-0.18 Micron Chips,” Applied Materials, Feb. 28, 2000, describes a successful evaluation of Applied Materials, Inc.'s Black Diamond™ material (a family of low-k products deposited using the DLK chamber) for production of advanced interconnect structures in copper sub-0.18 micron devices.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel CVD low-k material, and a method of making same, that overcomes the disadvantages of the present low-k materials used with copper dual damascene structures.
Another object of the present invention is to provide a novel CVD low-k material, and a method of making same, whose dielectric constant remains stable despite further processing.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.


REFERENCES:
patent: 5817572 (1998-10-01), Chiang et al.
patent: 6004883 (1999-12-01), Yu et al.
patent: 6007733 (1999-12-01), Jang et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6013581 (2000-01-01), Wu et al.
patent: 6207555 (2001-03-01), Ross
patent: 6211068 (2001-04-01), Huang
patent: 6255232 (2001-07-01), Chang et al.
patent: 6333256 (2001-12-01), Sandhu et al.
patent: 6350682 (2002-02-01), Liao
L. Peters, “Pursuing the Perfect Low-K Dielectric,” Semi-Conductor International, Sep. 1998, pp. 64-74.
“International Sematech Validates Manufacturing Capability of Applied Material's Low-K Solution for Copper Interconnects—Successful Results Achieved with Black Diamond for Production of Sub-0.18 Micron Chips”, Applied Materials, Feb. 28, 2000.

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