Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-07
2002-10-01
Sherry, Michael (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S266000, C438S593000, C438S594000, C438S763000, C438S689000, C438S695000, C438S706000, C438S725000
Reexamination Certificate
active
06458655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices and particularly to methods of manufacturing semiconductor devices including a step of dry etch and wet etch provided successively. The present invention also relates to methods of manufacturing flash memories including a step of dry etch and wet etch provided successively. The present invention also relates to flash memories manufactured by such manufacturing methods. The present invention also relates to methods of manufacturing static random access memories (SRAMs).
2. Description of the Background Art
FIG. 11
shows a cross section of a memory cell of a conventional flash memory.
Referring to
FIG. 11
, in a surface of a semiconductor substrate containing a p dopant a p doped region
1
a
is formed. On semiconductor substrate
1
a floating gate
4
is formed with a tunnel oxide film
3
posed therebetween. In a surface of p doped region
1
a
on opposite sides of floating gate
4
, source/drain regions
2
a
and
2
b
are formed. On floating gate
4
an insulation film
8
is formed. On insulation film
8
a control gate
9
is formed. On semiconductor substrate
1
, insulation layers
10
and
11
are formed such that they cover control gate
9
.
The flash memory operates as described below.
In write operation, drain region
2
b
receives a drain voltage of approximately 6 to 8V and control gate
9
receives a gate voltage of approximately 10 to 15V. Source region
2
a
and semiconductor substrate
1
have a voltage held at a ground voltage. As such a current of several hundreds &mgr;A flows through a channel region
2
c
. Of the electrons flowing from source region
2
a
to drain region
2
b
, the electrons accelerated in a vicinity of drain region
2
b
becomes those with high energy (i.e., hot electrons). Such electrons flow in a direction indicated by an arrow
12
due to an electric field resulting from the gate voltage applied to control gate
9
, and are thus introduced into floating gate
4
. As such electrons accumulate in floating gate
4
, the transistor's threshold voltage is increased. Such threshold voltage higher than a predetermined value corresponds to a state. referred to as “0”.
In data erase operation, initially source region
2
a
receives a source voltage of approximately 10 to 15V and control gate
9
and semiconductor substrate
1
are held at a ground potential. Then, drain region
2
b
is floated, and an electric field resulting from the source voltage applied to source region
2
a
allows the electrons accumulated in floating gate
4
to flow in a direction indicated by an arrow
13
, passing through tunnel insulation film
3
into semiconductor substrate
1
. When the electrons accumulated internal to floating gate
4
are extracted, the transistor's threshold is increased. Such threshold voltage lower than a predetermined value corresponds to a state with data erased, referred to as “1”. Such erasure allows collective erasure of memory cells formed in a single semiconductor device. In read operation, control gate
9
receives a gate voltage of approximately 5V and drain region
2
b
receives a drain voltage of approximately 1 to 2V, and then if channel region
2
c
passes current or the transistor is ON then data is determined to be “1” and if channel region
2
c
does not pass current or the transistor is OFF then data is determined to be “0”.
A flash memory configured as described above is manufactured by a method as described below.
Initially, as shown in
FIG. 12
, an element isolating oxide film is formed on a semiconductor substrate
1
of monocrystalline silicon to isolate memory cells from each other, isolate transistors in peripheral circuitry from each other, and isolate the cells and the peripheral transistors from each other. Then p doped region
1
a
in which memory cells are to be formed is formed. Then the substrate's upper surface is oxidized to provide a tunnel insulation film
3
of silicon dioxide (SiO
2
).
Referring to
FIG. 13
, chemical vapor deposition (CVD) is employed to deposit polycrystalline silicon on tunnel insulation film
3
. The polycrystalline silicon only in the memory cell region is etched in an x direction (a direction horizontal relative to the plane of the figure, not shown) to form a floating gate
4
. Then, chemical vapor deposition is similarly employed to form an insulation film
8
, such as a silicon nitride (SiN) film, a silicon oxide film. Then, insulation film
8
, the polycrystalline silicon and tunnel insulation film
3
are removed in the peripheral-circuitry region. Then, as in forming polycrystalline silicon (floating gate)
4
, chemical vapor deposition is employed to deposit polycrystalline silicon serving as control gate
9
.
Then, as shown in
FIG. 14
, on a region with polycrystalline silicon that is desired as a gate electrode a patterned photoresist
14
is provided in a y direction (a direction vertical relative to the plane of the figure). With patterned photoresist
14
used as a mask, the region is anisotropically etched to expose a surface of tunnel insulation film
3
.
Then, patterned resist
14
is for example plasma-ashed and thus removed.
As shown in
FIG. 15
, dopant ions are introduced in a direction indicated by an arrow
15
to form at an upper portion of p doped region
1
a
heavily n doped regions (source/drain regions)
2
a
and
2
b
higher in dopant concentration than p doped region
1
a
. Then, as shown in
FIG. 11
, chemical vapor deposition or the like is employed to provide insulation layers
10
and
11
formed of silicon oxide film and serving as a passivation film to complete a flash memory.
The semiconductor device manufacturing method as above has a disadvantage described below with reference to simplified drawings.
As shown in
FIG. 16
, on a silicon substrate
1
a SiO
2
film
2
is formed. On SiO
2
film
2
a polysilicon film
3
is deposited. On polysilicon film
3
a patterned photoresist
4
is provided by photolithography. With patterned resist
4
used as a mask, polysilicon film
3
is dry-etched and then successively SiO
2
film
2
is etched with a hydrofluoric acid solution.
In the hydroflouric acid solution process, however, when polysilicon film
3
is dry-etched an altered surface layer
5
of patterned photoresist
4
is removed, as shown in FIG.
17
. Removed surface layer
5
of the resist adheres onto silicon substrate
1
and thus disadvantageously prevents the underlying SiO
2
film
2
from being etched. Furthermore, removed surface layer
5
of the resist disadvantageously flows into the hydrofluoric acid treatment bath and as a foreign matter contaminates the bath.
Furthermore, such problem tends to occur particularly when polysilicon is etched with chloride type gas.
Furthermore, such problem also tends to occur when with a polysilicon film having an insulation film such as SiO
2
film, SiN film deposited thereon the SiO
2
/SiN film is dry-etched, the polysilicon film is dry-etched and the SiO
2
film is then wet-etched with hydrofluoric acid solution successively.
SUMMARY OF THE INVENTION
The present invention has been made to solve such disadvantages as described above.
The present invention contemplates an improved semiconductor manufacturing method capable of preventing removal of an altered surface layer of a patterned photoresist.
The present invention also contemplates an improved flash memory manufacturing method preventing removal of an altered surface layer of a patterned photoresist.
The present invention also contemplates an improved static random access memory manufacturing method preventing removal of an altered surface layer of a patterned photoresist.
In accordance with the present invention in one aspect a semiconductor device manufacturing method includes the steps of: initially forming on a semiconductor substrate an insulation film and a conductive layer successively by either deposition or deposition followed by patterning (step
1
); forming a patterned
Shimizu Shu
Tanaka Tamotsu
Yano Takashi
Yuzuriha Kojiro
Kilday Lisa
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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