Method of fabricating non-volatile memory devices integrated...

Details Method of fabricating non-volatile memory devices integrated... Method of fabricating non-volatile memory devices integrated...

2000-05-19

2002-10-01

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06458659

ABSTRACT:

TECHNICAL FIELD
This invention relates to an improved method of fabricating non-volatile memory devices integrated in a semiconductor substrate and organized into memory matrices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices integrated in a semiconductor substrate include matrices of memory cells, with each cell comprising at least one floating-gate MOS transistor and control circuitry made from fast-logic MOS transistors.
Each floating-gate MOS transistor conventionally includes a drain region and a source region which are formed in the semiconductor substrate and separated by a channel region. A floating gate electrode is provided above the substrate and separated from the substrate by a thin layer of gate oxide.
A control electrode is coupled capacitively to the floating gate electrode through a dielectric layer.
Considerable effort has been devoted in recent years to reducing the size of memory devices. These devices are presently fabricated using submicron technology processes.
These devices are often provided with isolating spacers on the side walls of the individual gate electrodes, which spacers allow the source/drain regions of the transistors provided in the memory device to be formed by an LDD implanting technique.
Forming the isolating spacers represents a highly critical step of the process of fabricating devices with submicron technology. This step typically includes depositing a dielectric layer onto the entire memory device surface, once the gate electrodes of the memory cells and the circuitry transistors have been formed. This dielectric layer is then partially etched back to produce the isolating spacers on the side walls of the gate electrodes.
A problem with the deposition of this dielectric layer and the following layer of filler oxide between adjacent gate electrodes is the appearance of holes in the resulting layer.
These holes mostly form themselves in the interspaces between cells of the memory matrix, where the gate electrodes lie fairly close together.
The appearance of these holes is ascribed to the difficulty of finding dielectrics which can fill gaps having an ever higher aspect ratio and exhibiting side walls in contact with the gate electrodes which are given ever steeper profiles.
These holes are receptive of contaminants and impurities from subsequent processing operations, and in the instance of memory devices, ultimately degrade the electrical performance of the individual memory cells therein.
Until now, no process was capable of providing a method wherein the gaps between the gate electrodes can be filled in an optimum manner and circuitry isolating spacers formed in one process step, while including appropriate features to ensure protection of the substrate portion where the memory matrix is being formed, and to overcome the limitations of conventional processes.
SUMMARY OF THE INVENTION
Embodiments of this invention provide in a standard process flow for fabricating non-volatile memory matrices for depositing a first dielectric layer followed by etching back this first layer to form isolating spacers in the matrix, as well as depositing a second dielectric layer, followed by etching back this second layer to form isolating spacers in the circuitry.
Specifically, embodiments of the invention include a method of fabricating non-volatile memory devices integrated in a semiconductor substrate which include at least one matrix of non-volatile memory cells, each having at least one floating-gate MOS transistor provided with a respective gate electrode and control circuitry associated with the matrix including MOS transistors provided with respective gate electrodes. The method of this embodiment includes depositing a first dielectric layer onto the entire exposed surface, etching back the first dielectric layer to form isolating spacers on the side walls of the gate electrodes of the matrix cells, depositing a second dielectric layer onto the entire exposed surface, overlying the memory matrix with a protective layer, and etching back the second dielectric layer to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors. Advantageously, the second dielectric layer is provided thinner than the first dielectric layer.
The invention relates, particularly but not exclusively, to a method of forming isolating spacers for memory cells of the EPROM or Flash EPROM type, and the description which follows will cover this field of application for convenience of explanation only.


REFERENCES:
patent: 5911105 (1999-06-01), Sasaki
patent: 5933730 (1999-08-01), Sun et al.
patent: 6258667 (2001-07-01), Huang

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