Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-01-14
2002-11-12
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
06480979
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit and test method, more particularly to efficient methods of testing a plurality of semiconductor integrated circuits concurrently.
Semiconductor integrated-circuit devices are tested by a type of automatic test equipment referred to below as a tester. A test is carried out by applying a set of control signals to input terminals of the device under test (DUT), and observing the response signals at output terminals of the DUT. In functional tests, which exercise the functions of the DUT, this procedure is repeated many times, using different sets of control signals.
Tests can be classified as single tests, in which one tester tests one device, and parallel tests, in which one tester tests two or more devices at once. Parallel tests can be carried out efficiently by connecting all of the devices under test to the same output terminals of the tester, and applying the same control signals to all devices simultaneously. Due to the shrinking process rules and growing complexity of semiconductor integrated circuits, which have progressed from large-scale integration (LSI) to very-large-scale integration (VLSI) and ultra-large-scale integration (ULSI), parallel testing has become necessary in order to shorten the test time per DUT, particularly in functional tests.
With conventional integrated circuits and test methods, in a parallel test, the tester still needs separate input terminals to receive the response signals from different devices. The total required number of input terminals is at least equal to the number of devices under test multiplied by the number of output terminals per DUT. Since a tester has a fixed number of input terminals, an increase in the number of output terminals per DUT must be offset by a decrease in the number of tested devices. Recent, highly complex semiconductor devices often have very large numbers of input and output terminals, so the number of devices that can be tested concurrently may be limited severely.
A related problem is that the time needed to process the response signals from a single DUT increases as the number of response signals increases. When a tester receives response signals from a plurality of devices, the response signals must generally be processed one DUT at a time, because of limited processing resources in the tester. The advantage of parallel testing is then diminished because the tester cannot process the response signals in parallel.
SUMMARY OF THE INVENTION
An object of the present invention is to increase the number of semiconductor integrated-circuit devices that a tester can test concurrently.
Another object of the invention is to shorten the time needed for processing the response signals from the devices under test.
According to a first aspect of the invention, a semiconductor integrated circuit comprises internal circuitry performing functions that the semiconductor integrated circuit provides as a product, and a selection circuit. The selection circuit receives an external selection signal, provides external output of response signals from the internal circuitry when the external selection signal is in one state, and blocks external output of the response signals when the external selection signal is in another state. The selection circuit may also block input of control signals to the internal circuitry when the external selection signal is in the latter state.
The first aspect of the invention also provides a parallel test system in which a tester has multiple output terminals for sending selection signals individually to the devices under test, a single set of output terminals for sending control signals to all of the devices under test, and a single set of input terminals for receiving response signals from all of the devices under test. The devices are selected in turn, and response signals are received from one device at a time. The number of semiconductor integrated circuit devices that can be connected to the tester and tested concurrently is limited only by the number of selection signal output terminals.
According to a second aspect of the invention, a semiconductor integrated circuit comprises internal circuitry performing functions that the semiconductor integrated circuit provides as a product, and an internal test circuit. The internal test circuit receives an external test control code, tests the internal circuitry by generating control signals as directed by the test control code, receives response signals from the internal circuitry, decides whether the internal circuitry passes or fails, and provides external output of the pass/fail decision. The internal test circuit may also include a non-volatile memory circuit for storing the decision result.
In a parallel test system in the second aspect of the invention, the processing of response signals from the internal circuitry in all devices under test is carried out concurrently, in the devices themselves, and the pass/fail decisions are reached concurrently. The tester only has to read the pass/fail results from the devices under test. When a series of tests is carried out, the tester may read the pass/fail result of each test from each device, or wait and read the final pass/fail result of all the tests from each device. In either case, the test time is shortened. The number of devices that can be tested concurrently is also increased, because the tester only needs one pass/fail decision input terminal per device, instead of a plurality of input terminals for response signals.
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patent: 6044481 (2000-03-01), Kornachuk et al.
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De'cady Albert
Harris Cynthia
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
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