Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-07-11
2002-10-15
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S206000
Reexamination Certificate
active
06466499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device and, more particularly, to a sense amplifier fabricated using silicon on insulator (SOI) technology.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or “data”). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the capacitor is charged or discharged, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. “Access” typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one (logic high) or a binary zero (logic low).
Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, one of the digit lines will increase in level, typically to a supply voltage Vcc, and the other digit line will decrease in level, typically to a ground level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.
FIG. 1
illustrates a sense amplifier
10
of a DRAM device having a first array ARRAY
0
20
and a second array ARRAY
1
22
, each of which comprises a plurality of memory cells
21
(shown in ARRAY
0
20
). As is generally known in the art, the term sense amplifier includes a collection of circuit elements connected to the digit lines of a DRAM array. This collection typically includes isolation transistors, devices for equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and devices connecting selected digit lines to input/output signal lines as will be described below.
As shown in
FIG. 1
, sense amplifier
10
includes a P-sense amplifier
70
and an N-sense amplifier
80
for sensing charge stored in the selected memory cell of the selected array
20
,
22
via a voltage differential on the pair of digit lines D
0
24
and D
0
*
26
. One of the arrays
20
,
22
is selected by application of signals ISOa and ISOb to transistors
32
a
,
32
b
and
34
a
,
34
b
, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors
32
a
and
32
b
become conductive, i.e., turn on, to connect ARRAY
0
20
to P-sense amplifier
70
and N-sense amplifier
80
while transistors
34
a
and
34
b
do not conduct, i.e., turn off, to isolate ARRAY
1
22
from P-sense amplifier
70
and N-sense amplifier
70
. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors
34
a
and
34
b
turn on to connect ARRAY
1
22
to P-sense amplifier
80
and N-sense amplifier
70
while transistors
32
a
and
32
b
turn off to isolate ARRAY
0
20
from P-sense amplifier
80
and N-sense amplifier
70
.
Equilibration circuits
50
a
and
50
b
are provided to equilibrate the digit lines D
0
24
and D
0
26
. Equilibration circuit
50
a
includes transistor
54
with a first source/drain region coupled to digit line D
0
24
, a second source/drain region coupled to digit line D
0
*
26
and a gate coupled to receive an equilibration signal EQa. Equilibration circuit
50
a
further includes first and second transistors
56
and
58
. Transistor
56
includes a first source/drain region that is coupled to digit line DO
24
, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to receive an equilibration voltage Veq, which, as noted, is typically equal to Vcc/2. Second transistor
58
includes a first source/drain region that is coupled to digit line D
0
*
26
, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQa is at a high logic level, equilibration circuit
50
a
effectively shorts digit line D
0
24
to digit line D
0
*
26
such that both lines are equilibrated to the voltage Veq. Equilibration circuit
50
b
is constructed in a similar manner to equilibration circuit
50
a
and operates when the EQb signal is at a high logic level.
When P-sense amplifier
70
and N-sense amplifier
80
have sensed the differential voltage across the digit lines D
0
24
and D
0
*
26
(as described below), a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O
36
and I/O*
38
by connecting the I/O lines I/O
36
and I/O*
38
to the digit lines D
0
24
and D
0
*
26
, respectively. A column select (CSEL) signal is applied to transistors
40
,
42
to turn them on and connect the digit lines D
0
24
and D
0
*
26
to the I/O lines I/O
36
and I/O*
38
.
The operation of the P-sense amplifier
80
and N-sense amplifier
70
is as follows. These amplifiers work together to detect the access signal voltage and drive the digit lines D
0
24
and D
0
*
26
to Vcc and ground accordingly. As shown in
FIG. 1
, the N-sense amplifier
80
consists of cross-coupled NMOS transistors
82
,
84
and drives the low potential digit line to ground. Similarly, the P-sense amplifier
70
consists of cross-coupled PMOS transistors
72
,
74
and drives the high potential digit line to Vcc. The NMOS pair
82
,
84
or N-sense-amp common node is labeled RNL*. Similarly, the P-sense-amp
70
common node is labeled ACT (for ACTive pull-up). Initially, RNL* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D
0
24
and D
0
*
26
are both initially at Vcc/2 volts, the N-sense-amp transistors
82
,
84
remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors
72
,
74
remain off due to their negative Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair
24
,
26
when the memory cell access o
Dickstein , Shapiro, Morin & Oshinsky, LLP
Dinh Son T.
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