Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2001-09-25

2002-12-31

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000

Reexamination Certificate

active

06500720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure of a semiconductor device, and more particularly to a method of manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a structure thereof.
2. Description of the Background Art
With miniaturization of semiconductor devices, a technique of forming a metal silicide for use in gate, source and drain has been in actual use as one of attempts to increase drain currents of a MOSFET for high-speed operation of circuits. A characteristic feature of the metal silicide lies in its lower resistance value than that of a doped polysilicon. In order to form the metal silicide, a refractory metal film is deposited on a silicon and then a heat treatment such as RTA (Rapid Thermal Annealing) is performed to react the silicon with the refractory metal film. Forming the metal silicide for use in the gate, source and drain lowers the resistance values of the respective regions, thereby increasing the drain currents.
Among kinds of metal suicides well known are a titanium silicide (TiSi
2
), a tungsten silicide (WSi
2
), a nickel silicide (NiSi), a platinum silicide (PtSi), a cobalt silicide (CoSi
2
) and the like. Among them, it is known that even when used in a fine gate electrode whose gate length is 0.1 &mgr;m or less, the cobalt silicide can lower the resistance of the gate electrode. On the other hand, it is known that when used in a gate electrode whose gate length is 0.15 &mgr;m or less, the tungsten silicide increases the resistance of the gate electrode by the linewidth effect. The cobalt silicide, nickel silicide or platinum silicide does not have the linewidth effect.
Now, reaction of cobalt (Co) with silicon (Si) will be discussed. At 400° C., Co begins to react with Si, thereby forming a Co
2
Si, and the sheet resistance gradually becomes higher. At 450 to 500° C., a CoSi is formed and the sheet resistance becomes maximum. Over 600° C., a CoSi
2
is formed and the sheet resistance becomes lower.
In the process of forming the cobalt silicide, first, a first RTA is performed at 450 to 600° C. Next, an unreacted Co is removed and then a second RTA is performed at 650 to 800° C. to lower the sheet resistance. Further, when the temperature for the second RTA rises up to 900° C., as the Co in the metal silicide is diffused into a silicon substrate, reaching the vicinity of a pn junction of source/drain regions, the amount of leakage currents increases.
FIG. 28
is a cross section showing a structure of a general-type MOSFET in which the cobalt silicide is formed. In an upper surface of a silicon substrate
101
, an STI (Shallow Trench Isolation)
102
is selectively formed. On the upper surface of the silicon substrate
101
, a gate electrode
104
is selectively formed with a gate insulating film
103
interposed therebetween. On the gate electrode
104
, a cobalt silicide
106
is formed. Further, in the upper surface of the silicon substrate
101
formed are source/drain regions
111
which are paired with a channel region which is formed below the gate electrode
104
interposed therebetween, being in contact with side surfaces of the STI
102
. On the source/drain regions
111
, cobalt silicide layers
112
are formed. On side surfaces of the gate electrode
104
, sidewalls
109
are formed with first and second offset films
107
and
108
interposed therebetween.
The reaction of silicidation proceeds through diffusion of refractory metal towards the silicon. Therefore, as shown in
FIG. 28
, the cobalt intrudes into an interface between the second offset film
108
and the silicon substrate
101
, to form an intruding portion
114
of the cobalt silicide layer
112
. Further, the cobalt intrudes into an interface between the STI
102
and the silicon substrate
101
, to form an intruding portion
115
of the cobalt silicide layer
112
.
With miniaturization of the semiconductor devices, when the width of the sidewall
109
becomes 10 nm or less, the intruding portion
114
of the cobalt silicide layer
112
reaches the gate insulating film
103
and the amount of leakage currents at the gate thereby increases. Further, when the depth of the pn junction formed at an interface between the source/drain region
111
and the silicon substrate
101
becomes shallower than the depth of 0.05 &mgr;m from the upper surface of the silicon substrate
101
, the intruding portion
115
of the cobalt silicide layer
112
reaches a depletion layer of the pnjunction and the amount of leakage currents at the source and drain thereby increases.
Furthermore, in a reaction process of silicidation, the metal silicide sometimes abnormally grows like a spike due to a stress in the phase transition of crystal, and the like. In
FIG. 28
shown is an abnormally-grown spike
113
of the cobalt silicide. The cobalt silicide abnormally grows at the temperature of 400 to 450° C., to form the spike
113
. With miniaturization of the semiconductor devices, when the depth of the pn junction formed at the interface between the source/drain region
111
and the silicon substrate
101
becomes shallower than the depth of 0.1 &mgr;m from the upper surface of the silicon substrate
101
, the spike
113
reaches the depletion layer of the pn junction and the amount of leakage currents at the source and drain thereby increases.
As one of methods for suppressing generation of the spike which is caused by abnormal growth of the cobalt silicide well known is a preamorphization method. In this method, nitrogen or germanium is ion-implanted to amorphize the silicon substrate in advance before a cobalt film is deposited, and then the cobalt silicide is formed. Preamorphization of the silicon substrate relieves a stress caused at an interface between the silicide and the silicon on reaction, to suppress generation of the spike.
FIGS. 29
to
35
are cross sections showing a method of manufacturing an N-type MOSFET by the preamorphization method in the background art step by step. Referring to
FIG. 29
, first, the STI
102
is selectively formed in the upper surface of the silicon substrate
101
. Subsequently, ion implantation is performed to form a well, a channel stopper layer and a channel dope layer (all not shown). Next, a silicon oxide film
120
is formed on the upper surface of the silicon substrate
101
. Subsequently, an amorphous silicon film
121
is entirely deposited by the CVD (Chemical Vapor Deposition) method. Then, phosphorus ions
122
are implanted into the amorphous silicon film
121
by ion implantation.
Referring to
FIG. 30
, in the next step, the amorphous silicon film
121
and the silicon oxide film
120
are patterned by photolithography and anisotropic dry etching, to form the gate electrode
104
and the gate insulating film
103
. Subsequently, a silicon-oxide-based insulating film such as a TEOS (Tetra Ethyl Ortho Silicate) film
123
is entirely deposited by the CVD method. With the temperature at this deposition, the amorphous silicon of the gate electrode
104
begins to become polysilicon (i.e., polycrystallize).
Referring to
FIG. 31
, in the next step, the TEOS film
123
is anisotropically etched, to form the first offset films
107
on the side surfaces of a gate structure consisting of the gate insulating film
103
and the gate electrode
104
. Subsequently, arsenic ions
124
are implanted, to form extension regions
110
in the upper surface of the silicon substrate
101
. Further, boron ions
125
are implanted, to form a pocket implantation region (not shown) in the silicon substrate
101
. Forming the first offset film
107
is intended to protect the gate insulating film
103
in the ion implantation, to reduce variation in threshold voltage by increasing the effective channel length Leff and reduce the capacitance (gate overlap capacitance) formed between the gate electrode
104
and the extension region
110
. Further, forming the pocket implantation region relieves roll-off of the threshold voltage and al

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