Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-16
2002-10-29
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S618000, C438S623000, C438S624000
Reexamination Certificate
active
06472312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to dielectric layers, as employed within microelectronic fabrications. More particularly, the present invention relates to methods for inhibiting microelectronic damascene processing induced physical degradation of dielectric layers, and in particular low dielectric constant dielectric layers, as employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, in comparison with conventional dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, such as but not limited to conventional silicon oxide dielectric materials, conventional silicon nitride materials and conventional silicon oxynitride materials as employed for forming microelectronic dielectric layers within microelectronic fabrication, where such conventional dielectric materials typically have a dielectric constant. Such comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications may include, but are not limited to, spin-on-polymer (SOP) dielectric materials, spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials, fluorosilicate glass (FSG) dielectric materials and aerogel (i.e., air entrained) dielectric materials.
Comparatively low dielectric constant dielectric materials are desirable within the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as within such applications comparatively low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced microelectronic fabrication patterned conductor layer parasitic capacitance and reduced microelectronic fabrication patterned conductor layer cross-talk.
While comparatively low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, comparatively low dielectric constant dielectric constant dielectric materials are nonetheless not entirely without problems within microelectronic fabrications when employed for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications. In that regard, and insofar as comparatively low dielectric constant dielectric materials typically have compromised physical properties in comparison with conventional dielectric materials, microelectronic dielectric layers when employed within microelectronic fabrications and formed of comparatively low dielectric constant dielectric materials often suffer from microelectronic processing induced physical degradation, such as but not limited to cracking and delamination, when fabricating a microelectronic fabrication while employing a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
It is thus desirable in the art of microelectronic fabrication to provide methods through which microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials may be fabricated within microelectronic fabrications with inhibited microelectronic fabrication processing induced physical degradation.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic dielectric layers, and in particular microelectronic dielectric layers formed of low dielectric constant dielectric materials, with desirable properties in the art of microelectronic fabrication.
For example, Chen et al., in U.S. Pat. No. 5,973,387, discloses a method for reducing within a gap filling microelectronic dielectric layer formed interposed between a series of patterns which comprises a densely patterned microelectronic conductor layer formed over a microelectronic substrate employed within a microelectronic fabrication a cracking at a juncture of: (1) the series of patterns which comprises the densely patterned microelectronic conductor layer; and (2) an open area of the microelectronic substrate. To realize the foregoing object, the method employs within a pattern which comprises the densely patterned microelectronic conductor layer, where the pattern in turn adjoins the open area of the microelectronic substrate, a sidewall tapered in the direction of the open area of the microelectronic substrate.
In addition, Zhao, in U.S. Pat. No. 6,071,809, discloses a method for fabricating within a microelectronic fabrication a dual damascene structure formed employing a microelectronic dielectric layer formed of a low dielectric constant dielectric material, wherein there is avoided within the dual damascene structure delamination of the microelectronic dielectric layer when forming within the dual damascene structure a chemical mechanical polish (CMP) planarized patterned microelectronic conductor layer which also comprises the dual damascene structure. To realize the foregoing object, the method employs formed upon the microelectronic dielectric layer when forming the dual damascene structure a composite hard mask layer comprising a silicon nitride hard mask material having formed thereupon a silicon oxide hard mask material, wherein the silicon oxide hard mask material serves as a sacrificial mask material when chemical mechanical polish (CMP) planarizing within the dual damascene structure the chemical mechanical polish (CMP) planarized patterned microelectronic conductor layer within the dual damascene structure.
Further, Shields, in U.S. Pat. No. 6,084,290, discloses a microelectronic fabrication and a method for fabricating the microelectronic fabrication, wherein there is formed within the microelectronic fabrication an interlayer microelectronic dielectric layer formed of a hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material absent cracking within the interlayer microelectronic dielectric layer formed of the hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material. To realize the foregoing object, the interlayer microelectronic dielectric layer formed of the hydrogen silsesquioxane (HSQ) low dielectric constant dielectric material is formed within the microelectronic fabrication upon a planar substrate layer, rather than a topographic substrate layer.
Finally, Sabota et al., in U.S. Pat. No. 6,133,619, discloses a microelectronic fabrication and a method for fabricating the microelectronic fabrication, wherein the microelectronic fabrication comprises a microelectronic dielectric layer formed of a low dielectric constant hydrogen silsesquioxane (HSQ) dielectric material formed interposed between a series of patterns which comprises a patterned microelectronic conductor layer within the microelectronic fabrication, and wherein there is reduced a hydrogen silsesquioxane (HSQ) dielectric material outgassing induced delamination of an upper lying barrier dielectric layer formed upon an upper lying patte
Bao Tien-I
Chang Weng
Jang Syun-Ming
Nguyen Thanh
Nguyen Tuan H.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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