Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-03-31
2002-12-10
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000, C714S033000, C703S017000, C709S241000, C716S030000
Reexamination Certificate
active
06493841
ABSTRACT:
MICROFICHE APPENDIX
This patent includes a Microfiche Appendix which consists of a total of 5 microfiche that contain a total of 442 frames.
FIELD OF THE INVENTION
The present invention relates generally to verification languages, and more particularly to language statements which verify whether a system under test has responded to a stimulus with certain expected values.
BACKGROUND OF THE INVENTION
To tackle the increasing complexity of integrated digital electronic circuits, designers need faster and more accurate methods for verifying the functionality and timing of such circuits, particularly in light of the need for ever-shrinking product development times.
The complexity of designing such circuits is often handled by expressing the design in a high-level hardware description language (HLHDL). The HLHDL description is then converted into an actual circuit through a process, well known to those of ordinary skill in the art as “synthesis,” involving translation and optimization. Typical examples of an HLHDL are IEEE Standard 1076-1993 VHDL and IEEE Standard 1364-1995 Verilog HDL, both of which are herein incorporated by reference.
An HLHDL description can be verified by simulating the HLHDL description itself, without translating the HLHDL to a lower-level description. This simulation is subjected to certain test data and the simulation's responses are recorded or analyzed.
Verification of the HLHDL description is important since detecting a circuit problem early prevents the expenditure of valuable designer time on achieving an efficient circuit implementation for a design which, at a higher level, will not achieve its intended purpose. In addition, simulation of the design under test (DUT) can be accomplished much more quickly in an HLHDL than after the DUT has been translated into a lower-level, more circuit oriented, description.
The verification of HLHDL descriptions has been aided through the development of Hardware Verification Languages (or HVLs). Among other goals, HVLs are intended to provide programming constructs and capabilities which are more closely matched to the task of modeling the environment of an HLHDL design than are, for example, the HLHDL itself or software-oriented programming languages (such as C or C++). HVLs permit a DUT, particularly those DUTs expressed in an HLHDL, to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT.
SUMMARY OF THE INVENTION
The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL.
More specifically, the present invention relates to an HVL capability, known as an “expect,” for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance.
In particular, the present invention relates to a form of expect referred to as “restricted.” When a restricted expect is first executed as part of a Vera language program, an initial check is made to determine whether the DUT's nodes monitored by the expect have the anticipated values. If these nodes do, then the restricted expect is considered to have been satisfied, and processing of the Vera language program continues with the next statements in its flow of control. If the expect is not satisfied immediately, it will then check whether a window of time has been specified during which it may still be satisfied. If no window of time is specified, then the expect is not satisfied and a “simulation error” is generated. If a window of time is specified, then during that time period the expect will monitor for the first transition on any of the nodes whose value it is programmed to check. At the time of this first transition, if the DUT's nodes do correspond to the expected values, then the expect is satisfied. If the DUT's nodes do not correspond to the expected values, then the expect is not satisfied and a simulation error is generated. If, upon the conclusion of the window period, no transition has occurred on any of the nodes monitored by the expect, then the expect is also not satisfied and a simulation error is generated. An offset “delay” may also be specified, which will delay any monitoring by the expect, as well as any action which the expect might take as a result of that monitoring, for a specified time period.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.
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Bertacco Valeria Maria
Chapiro Daniel Marcos
Kim Won Sub
Pintz Sandro Hermann
Howrey Simon Arnold & White , LLP
Kaplan Jonathan T.
Moise Emmanuel L.
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