Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-23
2002-11-05
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000
Reexamination Certificate
active
06475864
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a vertical semiconductor structure, applicable to semiconductor devices such as MOSFETs (insulated gate field effect transistors), IGBTs (insulated gate bipolar transistors), bipolar transistors and diodes, that facilitates realizing a high breakdown voltage and a high current capacity. The present invention relates also to a semiconductor device including such a vertical semiconductor structure and the method of manufacturing such a semiconductor device.
BACKGROUND ART
The semiconductor devices may be roughly classified into a lateral semiconductor device that arranges its electrodes on a major surface and a vertical semiconductor device that distributes its electrodes on both major surfaces facing opposite to each other. When the vertical semiconductor device is ON, a drift current flows in the thickness direction of the semiconductor chip (vertical direction). When the vertical semiconductor device is OFF, the depletion layers caused by applying a reverse bias voltage expand also in the vertical direction.
FIG. 51
is a cross sectional view of a conventional planar-type n-channel MOSFET.
Referring now to
FIG. 51
, the vertical MOSFET includes an n
+
-type drain layer
51
with low electrical resistance, a drain electrode
58
in electrical contact with n
+
-type drain layer
51
, a highly resistive n-type drift layer
52
on n
+
-type drain layer
51
, p-type base regions
53
formed selectively in the surface portion of n-type drift layer
52
, a heavily doped n
+
-type source regions
54
formed selectively in p-type base regions
53
, a gate insulation film
55
on the extended portion of p-type base regions
53
extended between n
+
-type source region
54
and n-type drift layer
52
, a gate electrode layer
56
on gate insulation film
55
, and a source electrode
57
in contact commonly with n
+
-type source regions
54
and p-type base regions
53
.
In the vertical semiconductor device shown in
FIG. 51
, highly resistive n-type drift layer
52
works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. In the OFF-state of the MOSFET, n-type drift layer
52
is depleted to obtain a high breakdown voltage. Shortening the current path in highly resistive n-type drift layer
52
is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered in the ON-state of the device. However, the short current path in n-type drift layer
52
lowers the breakdown voltage (the voltage between the drain D and the source S), since the width between the drain D and the source S, for that the depletion layers expand from the pn-junctions between p-type base regions
53
and n-type drift layer
52
, is narrowed and the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon.
However, in the semiconductor device with a high breakdown voltage, a thick n-type drift layer
2
inevitably causes high on-resistance and loss increase. Thus, the breakdown voltage or the on-resistance is improved at the sacrifice of the on-resistance or the breakdown voltage. In short, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the MOSFET. The tradeoff relation exists in the other semiconductor devices such as IGBTs, bipolar transistors and diodes. The tradeoff relation exists also in lateral semiconductor devices, in that the flow direction of the drift current in the ON-state of the devices is different from the expansion direction of the depletion layers expanded by a reverse bias voltage applied in the OFF-state of the devices.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose semiconductor devices include an alternating conductivity type drift layer formed of heavily doped n-type regions and p-type regions alternately laminated with each other. The alternating conductivity type drift layer is depleted to bear the breakdown voltage in the OFF-state of the device.
FIG. 52
is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to
FIG. 52
, the vertical MOSFET of
FIG. 52
is different from the vertical MOSFET of
FIG. 51
in that the vertical MOSFET of
FIG. 52
includes a drift layer
62
, that is not a single-layered one but formed of n-type first semiconductor regions
62
a
and p-type second semiconductor regions
62
b
alternately laminated with each other. In the figure, p-type well regions
63
, n
+
-type source regions
64
, gate insulation films
65
, gate electrode layers
66
, a source electrode
67
, and a drain electrode
68
are shown.
The drift layer
62
is formed in the following way. A highly resistive n-type layer is epitaxially grown on an n
+
-type drain layer
61
used as a substrate. Trenches are dug through the n-type layer down to n
+
-type drain layer
61
by selective etching, leaving n-type first semiconductor regions
62
a
. Then, p-type second semiconductor regions
62
b
are formed by epitaxially growing p-type layers in the trenches.
Thus, the vertical semiconductor device shown in
FIG. 52
, in that a current flows between the electrodes arranged on two major surfaces facing opposite to each other, has a laminate-type drift layer of alternating conductivity types formed of first semiconductor regions of a first conductivity type, that provide a current path in the ON-state of the semiconductor device and are depleted in the OFF-state of the semiconductor device, and second semiconductor regions of a second conductivity types.
Hereinafter, the semiconductor device including an alternating conductivity type drift layer will be referred to as the “super-junction semiconductor device”.
In the super-junction semiconductor device, the tradeoff relation between the on-resistance R
ON
A and the breakdown voltage V
B
is expressed theoretically by the following relational expression (1).
R
ON
A
=(4
dV
B
)(&mgr;
O
&egr;
S
E
C
2
) (1)
Here, &mgr; is the electron mobility, &egr;
O
the dielectric permeability of the vacuum, &egr;
S
the relative dielectric permeability of silicon, d the width of the n-type drift region, and E
C
the critical electric field strength.
As the relational expression (1) indicates, the on-resistance of the super-junction semiconductor device increases merely in proportion to the breakdown voltage. When the breakdown voltage is raised, the on-resistance is not increased so greatly. The onresistance is reduced, at a fixed breakdown voltage, by narrowing the n-type first semiconductor regions.
A method of manufacturing a super-junction semiconductor device with an excellent mass-productivity is disclosed in Japanese Unexamined Laid Open Patent Application 2000-40822. According to the method disclosed in the above identified patent application, at least first semiconductor regions of the first conductivity type or second semiconductor regions of the second conductivity type are formed through one or more steps of epitaxial growth, one or more steps of ion implantation and one or more steps of heat treatment.
According to the method described above, however, an alternating conductivity type layer is formed by repeating the steps of epitaxial growth, ion implantation and heat treatment, and, then, the electrode means of the MOSFET are formed on the side of the first major surface and on the side of the second major surface. Since it is difficult for the method described above to conduct formation of the alternating conductivity type layer and to conduct formation of the device structure on the sides of the major surfaces individually, manufacturing steps are increased and complicated, causing manufacturing costs increase. Since it is indispensable to conduct heat treatment for forming the device structure on the side of the first major surface, the alternating co
Fujihira Tatsuhiko
Iwamoto Susumu
Kunihara Kenji
Onishi Yasuhiko
Sato Takahiro
Elms Richard
Fuji Electric & Co., Ltd.
Owens Beth E.
Rossi & Associates
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