Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-09-01
2002-12-24
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S536000, C257S537000, C257S758000, C257S762000
Reexamination Certificate
active
06498385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit (IC) chips which can be tailored to produce a fuse. The invention further relates to a method of making an improved non-corrosive resistive structure.
2. Related Art
Fuses can be used in semiconductor chips to provide redundancy, electrical chip identification and customization of function. For designs having three (or more) layers of wiring, the fuses are typically formed from a segment of one of the wiring layers, e.g., the “last metal” (LM) or “last metal minus one” (LM−
1
) wiring layer. Fusing, i.e., the deletion of a segment of metal fuse line, is accomplished by exposing the segment of metal fuse line to a short, high intensity pulse of “light” from an infra-red (IR) laser. The metal line absorbs energy, melts and expands, and ruptures any overlain passivation layer. The molten metal then boils or vaporizes out of its oxide surroundings, disrupting line continuity and causing high electrical resistance. Metals exposed by this laser deletion process can corrode possibly leading to undesirable reconnection of a fuse link.
Semiconductor integrated circuits are formed in a body of semiconductor material having active regions which are joined in a desired circuit configuration by a plurality of wiring layers laid down on the surface of the body.
In the manufacture of the circuits, wiring layers are deposited and defined and interconnected with conductive vias through a series of well known photolithography and metal etching steps. Each such wiring level can be coated with a layer of a glassy protective material, known as a passivation layer, which protects and insulates the wiring of each layer. The creation of integrated circuits with such multiple wiring layers is well known to the semiconductor art.
In some circuits, such as, e.g., CMOS logic circuits, the fuses designed in the circuit are often formed in regular arrays in the upper most layers of wiring and in a position such that other wiring is not placed immediately over the fuses. In such arrays the fuses are often aligned in parallel rows and placed as closely together as is possible. By opening selected ones of these fuses the logic elements of the circuits can be arranged in different combinations to perform different logic functions.
These fuses are typically opened by applying a laser pulse of sufficient size, duration and power as to superheat and vaporize the metal forming the fuse. This superheating of the fuse and its vaporization fractures and blows away a portion of the overlying glassy protective layer creating a saucer shaped crater in the protective layer. When the protective layer ruptures, cracks can radiate outwardly causing additional damage such as breakage of or the uncovering of adjacent elements. Such uncovering of the adjacent elements can cause subsequent corrosion and premature failure of the circuit.
It is desirable that in future generation integrated circuits, such as, e.g., sub-0.25 &mgr;m complimentary metal oxide semiconductor (CMOS) back end of line (BEOL), that copper (Cu) wiring be employed to meet BEOL resistor capacitor (RC) delay performance requirements. During stressing of copper fuses, such as under conditions of, e.g., in 85 degrees celsius (C) temperature, 85% relative humidity with electrical bias stressing, copper fuses can corrode. This corrosion may extend through multiple via levels if a Tantalum Nitride/Tantalum (TaN/Ta) liner does not act as a corrosion stop. The byproduct of this corrosion can completely cover the blown fuse area which can create an undesirable resistive leakage path between blown fuses. Known methods of reducing or eliminating this defect include using aluminum wiring and passivating the copper fuse after fuseblow. However, adding an aluminum wiring level reduces the electrical performance of the device and adding a passivation layer after fuseblow increases cost and complexity. An improved method to reduce or eliminate corrosion of exposed copper wiring is desired.
The reader is referred to the following patents related to fuses including:
“Fusible Links with Improved Interconnect Structure,” U.S. Pat. No. 5,760,674;
“Array Fuse Damage Protection Devices and Fabrication Method,” U.S. Pat. No. 5,420,455, to Richard A. Gilmour, et al.;
“Integrated Pad and Fuse Structure for Planar Copper Metallurgy,” U.S. Pat. No. 5,731,624, to William T. Motsiff, et al.;
“Method of making a multilayer thin film structure,” U.S. Pat. No. 5,266,446, to Kenneth Chang, et al.; the contents of which are incorporated herein by reference in their entirety.
The reader is also referred to several articles, published patent documents and patents:
Anon., “Fuse Structure for Wide Fuse Materials Choice,” IBM Technical Disclosure Bulletin, Vol. 32, No. 3A, August 1989, pp. 438-439;
Anon., “Optimum Metal Line Structures for Memory Array and Support Circuits,” IBM Technical Disclosure Bulletin, Vol. 30, No. May 12, 1988, pp. 218-219;
Anon., “Method to Incorporate Three Sets of Pattern Information in Two Photo-Masking Steps,” IBM Technical Disclosure Bulletin, Vol. 32, No. 8A, January 1990, pp. 170-171;
“Structure and Method of Making Alpha-Ta in Thin Films,” U.S. Pat. No. 5,281,485 to E. G. Colgan;
European Published Application EP 751566 A2, “A Thin-Film Metal Barrier for Electrical Connections,” to C. Cabral er al.
C. K. Hu et al., “Diffusion Barrier Studies for Cu,” Proc. V-MIC, 1986, pp. 181-187;
C. H. HU et al., “Copper-Polyimide Wiring Technology for VLSI Circuits,” Proc. Material Research soc., 1990, pp. 369-373; and
D. Edelstein et al., “Full Coper Wiring in a Sub-0.25 &mgr;m CMOS ULSI Technology,” Tech. Dig. IEEE Int. Electr. Dev. Mtg. 1997, pp. 773-776, the contents of which are incorporated herein by reference in their entirety.
Resistor elements are important for peripheral and internal circuits. Resistor elements can be used in internal circuits in, e.g., voltage regulators, reference bias circuits, and other applications. Resistor elements can be used in peripheral circuits in receiver and driver circuits for impedance matching, noise/ring-back dampening, resistor ballasting, overvoltage dampening and other applications. In electrostatic discharge (ESD) networks, resistors can be used in resistor capacitor (RC) coupled n-type field effect transistors (NFETs), integrated with metal oxide semiconductor FETs (MOSFETs) for resistor ballasting, and a plurality of other applications.
Many materials used as resistors are good in a functional regime but inadequate for ESD robustness or precision linear applications. Diffused resistors are commonly used in circuit applications, yet can have many disadvantages. Polysilicon film resistors, and diffused implanted resistors can have many concerns in high voltage and high current regimes. N-well, n-diffusion and buried resistors (BR) can be used in many circuit applications. Polysilicon resistors can also have reliability concerns. Polysilicon resistors can exhibit a “spaghetti effect” at high voltage stress. Under high voltage stress, polysilicon resistors can have a tendency to change resistance values causing misfunction of circuit and ESD applications.
N-well, n-diffusion and buried resistors (BR) can be used in many circuit applications. Diffused resistors can add extra capacitance to a circuit. This extra capacitance can be disadvantageous to receiver performance and driver capacitance loading. For analog, radio frequency CMOS and high performance applications, capacitance can be a concern. Diffused resistors can also be involved in ringing phenomenon (ring-back), undershoot phenomena, and latchup. For solid state transistor logic (SSTL) circuit applications where “critical dampening” is needed, e.g., in input/output (I/O) circuits, diffused elements can be detrimental to the ringing as they pass current in negative undershoot. N-well, n-diffusion, and buried resistors (BRs) can also form a parasitic npn structure that can create unwanted ESD and functional parasitic devices. As a result, ground rules
Daubenspeck Timothy H.
Edelstein Daniel C.
Geffken Robert M.
Motsiff William T.
Stamper Anthony K.
Crane Sara
International Business Machines - Corporation
Sabo William D.
LandOfFree
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