Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-03
2002-06-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000
Reexamination Certificate
active
06403412
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to DRAM cells; and, more particularly, to a method for forming a bottle shaped trench for use with such cells.
DESCRIPTION OF THE PRIOR ART
Recently, as the capacity of a semiconductor memory device such as a DRAM is increased towards 256 Mb and beyond, innovative cell concepts are needed to push the cell area to practical limits. One such concept is to place a trench storage capacitor partially under a cell's access device. Although cell structures using such concepts as the buried trench cell have been proposed in the past, these structures rely on expensive selective epi growth techniques to reduce the trench opening. Selective epi growth, however, typically has a very high defect density and therefore is generally considered to be unsuitable for DRAM applications.
To overcome the drawbacks associated with selective epi growth, there has been proposed a method for forming a bottle shaped trench. This method is disclosed in U.S. Pat. No. 5,658,816, issued on Aug. 19, 1997 and entitled “METHOD OF MAKING DRAM CELL WITH TRENCH UNDER DEVICE FOR 256 MB DRAM AND BEYOND”, by Rajeevakumar, in which a bottle shaped deep trench (DT) is fabricated through the use of reactive ion etching (RIE) and oxidation techniques as sketched hereinafter.
That is, referring to
FIG. 1A
, a trench
210
of a first depth is formed in a doped silicon substrate
200
with a lightly doped epitaxial layer
202
of silicon by using RIE, the trench
210
having an opening of a first cross sectional area at the surface of the substrate
200
. Next, nitride collar
212
is formed on the walls of the trench
210
of the first depth by blanketly depositing a layer of nitride on the structure including the trench
210
and then etching anisotropically using RIE to remove this nitride layer from horizontal surfaces.
As described in
FIG. 1B
, the trench
210
is then further etched to a second depth in the substrate
200
to thereby generate a deepened trench
310
.
The deepened trench
310
is now oxidized by thermal oxidation, resulting in an oxide layer
414
on the walls of the trench
310
, as shown in FIG.
1
C.
Then, referring to
FIG. 1D
, the deepened trench
310
is expanded to a second cross-sectional area by etching isotropically the oxide layer
414
using a buffered HF etch to thereby obtain a bottle shaped trench
510
. This process of oxidation of the trench followed by etching may require more than one iteration to achieve a desired final trench size.
As illustrated above, the above patent uses nitride collar and oxidation of the exposed silicon from the lower portion of the trench, followed by the wet etch (HF) strip of the oxide layer to expand the volume of the void in the trench.
However, the nitride collar is consumed during the above processes because the nitride film is converted slowly to oxide during the oxidation. Although the oxidation of the nitride film proceeds only at {fraction (1/25)} of the speed of oxidation of silicon, it is pretty obvious that the repeated oxidation will very soon wear the nitride very thin. Accordingly, once the nitride layer is used up, the silicon will be consumed from the upper portion of the trench and reduce the usable area for active area formation.
Furthermore, the thermal oxidation step in the above method could cause dislocations in the silicon substrate due to stress during the oxidation.
Thus a need has arisen for a DRAM cell structure that can take advantage of the area minimization benefits of the prior art trench-under-access device techniques, while avoiding the drawbacks associated with the selective epi growth and the oxidation techniques.
SUMMARY OF THE INVENTION
It is, therefore, one aspect of the present invention to provide a method for fabricating a bottle shaped trench by using gas phase HCl etching to isotropically etch silicon inside the trench.
It is another aspect of the present invention to obtain benefits of potential in-situ process integration with gas phase doping in the same tool as the one that performed the HCl etching process.
These and other aspects and advantages are achieved in the present invention by a method which includes gas phase etching and doping. The method of the present invention comprises the steps of:
(a) providing a substrate with a substantially vertical trench therein and a collar about an upper interior portion of the trench;
(b) gas phase etching a lower interior portion of the trench under the collar to allow the lower interior portion of the trench to be expanded, wherein the expanded lower interior portion has a wider cross section than that of the upper interior portion of the trench; and
(c) gas phase doping the substrate about the expanded lower interior portion of the trench.
REFERENCES:
patent: 4526631 (1985-07-01), Silvestri et al.
patent: 5225697 (1993-07-01), Malhi et al.
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5358601 (1994-10-01), Cathey
patent: 5658816 (1997-08-01), Rajeevakumar
patent: 6008104 (1999-12-01), Schrems
patent: 6018174 (2000-01-01), Schrems
Economikos Laertis
Park Byeongju
International Business Machines Corp.
Nelms David
Nhu David
Rosenman & Colin LLP
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