Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-01-29
2002-12-24
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C710S058000, C710S120000
Reexamination Certificate
active
06499086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to processors which include a data bus for communicating large amounts of data, such as video or graphics data, to a device on the bus, such as an external device. In particular, the invention concerns providing a dedicated bus that avoids the need for transmitting such information through other system buses.
2. Related Art
FIG. 1
is a block diagram of a conventional system. A central processing unit (CPU)
1
is connected through a data communication bus
3
to an interface
5
and a high level L2 cache memory
7
. L2 cache
7
communicates with another cache
8
over link
11
. The L2 cache
7
is connected to a memory control unit
9
. Bridge
17
links the system to PCI bus
19
. The PCI bus
19
has various elements connected thereto. These could include a double or quad speed CD ROM
21
, a graphics controller
23
and possibly a digital signal processor (DSP)
25
. Graphics controller
23
is also connected to memory
27
and is used to drive display
29
.
In a conventional system as shown in
FIG. 1
, compressed video is supplied from a video source, such as CD ROM
21
, under control of CPU
1
, onto PCI bus
19
. DSP
25
, under control of CPU
1
, processes the compressed video to create decompressed video for delivery to graphics control unit
23
for display of a corresponding image on display
29
.
Recent advances in video processing have improved the conventional system of
FIG. 1
to yield a system as shown in FIG.
2
. DSP
25
is no longer connected to PCI bus
19
, thus reducing the hardware and real estate needed to implement the system. Instead, digital signal processing is accomplished within CPU
1
.
The digital signal processing in CPU
1
can take either of two forms. A first form is the incorporation of a conventional DSP, such as DSP
25
, onto the microprocessor chip comprising CPU
1
. A second form is the use of processing wherein the activities previously accomplished by a DSP are accomplished by the CPU according to software. In either form, the incorporation of the DSP activities, such as the task of decompressing compressed video to produce decompressed video, into CPU
1
, can lead to drawbacks. As described below, these drawbacks are addressed by the invention.
For a conventional display
29
containing 1024 by 768 pixels, production of one high color image requiring 2 bytes per pixel requires about 1.6 megabytes of data. At 8 bits per byte, such an image requires about 12.5 M bits. To produce a full motion video image, a frame rate of 30 frames per second is required. Thus, production of a full motion 16 bit full color video image on display
29
requires about 48 megabytes of data per second.
In the system of
FIG. 2
, CPU
1
executes the decompression algorithm, and the decompressed video is routed through bridge
17
to PCI bus
19
. PCI bus
19
has a peak bandwidth of 133 megabytes, with about 50 megabytes usable. As noted above, a high color image requires 48 megabytes per second of decompressed video. A PCI bus has a peak capability of about 132 M bytes per second. However, this rate is not sustainable because bus overhead reduces the useable bus bandwidth to about 50 M bytes/sec. Since PCI bus
19
has a usable capability of only about 50 megabytes per second, production of decompressed video routed to graphics controller
23
consumes virtually all of the capability of PCI bus
19
, thereby leaving little bandwidth for use by other elements such as CD ROM
21
and DSP
25
. New 64 bit, 66 MHz PCI bus configurations are faster, but have other drawbacks. Such drawbacks include electromagnetic interference (EMI), increased cost and limits on the number of available slots per bridge, thereby requiring more bridges and further driving costs up.
In the conventional system of
FIG. 1
, the close physical proximity of DSP
25
to graphics controller
23
minimized the negative impact of the bus dominance by the decompressed video from DSP
25
to graphics controller
23
. However, in systems such as that of
FIG. 2
, wherein the digital signal processing is occurring in CPU
1
, this bus dominance leads to degradation of the video image.
For example, since more than two megabytes of bandwidth are needed for CD ROM
21
to provide the compressed video to CPU
1
, the result is that 48 megabytes of bandwidth on the PCI bus are not always available for the delivery of decompressed video to graphics controller
23
. When the decompressed video is not available to graphics controller
23
, one or more video frames may be dropped. When the frame rate falls below 30 frames per second, the resulting video image may appear degraded. To compensate for this situation, designers have opted to use only a portion of video display
29
, such as a window, to show full motion video. By using less (fewer pixels) of the display, a smaller bandwidth is required for the decompressed video, the frame rate can be maintained, and sufficient bus capacity exists to allow other devices to communicate via PCI bus
19
. However, the constraint of using only a portion of the available display for full motion video is limiting.
SUMMARY AND OBJECTS OF THE INVENTION
In view of the above limitations of the related art, it is an object of the invention to provide a system in which decompressed video can be transmitted to a display with a minimum of frame dropping and without incurring the disadvantages of conventional systems.
The above and other objects of the invention are accomplished by providing a separate bus from CPU
1
to graphics controller
23
over which decompressed video is transmitted. This separate bus eliminates communication through L2 cache
7
, the memory control unit
9
, bridge
17
, and PCI bus
19
. Implementation of a separate bus communicating between CPU
1
and graphics controller
23
according to the invention relieves the PCI bus of this communication requirement, thus providing additional PCI bus capability to facilitate communication between other elements of the system. Although the capability of PCI bus
19
is itself unaffected, the elimination of the decompressed video from PCI bus
19
results in more bandwidth being available for the other elements to communicate over this bus.
The high speed bus according to the invention can be a duplicate of the buses currently being used.
Preferably, however, the bus between the CPU
1
and the graphics controller
23
would be a serial high speed bus which would provide high bandwidth and low electro magnetic interference (EMI).
REFERENCES:
patent: 4684997 (1987-08-01), Romeo et al.
patent: 5212742 (1993-05-01), Normile et al.
patent: 5305443 (1994-04-01), Franzo
patent: 5392407 (1995-02-01), Heil et al.
patent: 5426739 (1995-06-01), Lin et al.
patent: 5450551 (1995-09-01), Amini et al.
patent: 5461679 (1995-10-01), Normille et al.
patent: 5566306 (1996-10-01), Ishida
patent: 5630078 (1997-05-01), Fuoco et al.
patent: 5721684 (1998-02-01), Takita
patent: 5898894 (1999-04-01), Gray et al.
Belt Steven L.
Dutton Drew J.
Gephardt Douglas D.
Stewart Brett B.
Wisor Rita M.
Advanced Micro Devices , Inc.
Thai Tuan V.
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