Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-23
2002-10-22
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S254000
Reexamination Certificate
active
06468858
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a metal—insulator—metal (MIM), capacitor structure for a dynamic random access memory (DRAM), device.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, has allowed the performance of these sub-micron devices to be increased while still maintaining, or even decreasing, the manufacturing costs for these same devices. Smaller semiconductor chips, still offering device densities equal to, or greater than, device densities achieved with larger size semiconductor chips, have allowed a greater number of the smaller semiconductor chips to be obtained from a specific size substrate, thus reducing the manufacturing cost for a specific chip. The smaller semiconductor chips however, such a dynamic random access memory (DRAM) chips, are now comprised with smaller individual transfer gate transistors, which in turn commit less horizontal space for the DRAM stacked capacitor structures, which directly overlay the transfer gate transistor. Therefore to satisfy capacitance requirements novel designs for DRAM capacitor structures, featuring increased vertical features needed to compensate for the decreased horizontal features now necessitated with sub-micron DRAM devices, have been employed. Storage node components, of DRAM capacitor structures, have been fabricated with fin type features, crown shaped features, and cylindrical shaped features, in an attempt to increase the surface area of a DRAM capacitor structure which now directly overlays a horizontally shrinking, underlying DRAM transfer gate transistor component.
However the processes used to fabricate DRAM capacitor structures, comprised with fin type, crown shaped, or cylindrical type features, although resulting in the desired increase in capacitor surface are, however do increase process complexity and cost. The present invention will describe a process for forming an MIM capacitor structure, for a DRAM device, in which a capacitor dielectric layer exhibiting a high dielectric constant is employed to increase capacitance when compared to counterpart capacitor structures, comprised with a lower dielectric constant, capacitor dielectric layer. The use of the higher dielectric constant, capacitor dielectric layer, in addition to its use in a cylindrical shaped capacitor structure, result in the increased capacitance required for the sub-micron DRAM devices, now employed in designs of a 256 MB or greater. However this invention will primarily feature the novel use of a noble metal plug structure, used underlying the capacitor structure, and formed using an electroless plating procedure which allows a voidless, noble metal plug structure to be obtained. Prior art, such as Lou in U.S. Pat. No. 6,159,793, describe a process for forming an MIM capacitor structure, however that prior art does not detail the materials, or process sequence, specifically the use of, and the method of forming, a noble metal plug structure, featured in this present invention.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a metal—insulator—metal (MIM), capacitor structure, for a DRAM device.
It is another object of this invention to use storage node structure comprised of platinum, and to form the platinum storage node structure in a capacitor opening, overlying and contacting an underlying platinum plug structure.
It is still another object of this invention to form a high dielectric constant, capacitor dielectric layer, such as BaTiO
3
, or Ta
2
O
5
, on the underlying platinum storage node structure.
It is still yet another object of this invention to use an electroless plating procedure to form a platinum plug structure on a landing pad exposed at the bottom of an opening in an insulator layer, prior to the formation of the overlying capacitor structure, with the landing pad comprised of tungsten, and comprised with an overlying ruthenium layer, used as a seed layer for the electroless platinum plating procedure.
In accordance with the present invention a process for forming a metal—insulator—metal (MIM), capacitor structure, overlying and contacting a platinum plug structure, in turn formed via electroless plating on a ruthenium seed layer, is described. A landing pad structure, comprised of a ruthenium seed layer overlying a tungsten layer, is defined either directly on a source/drain region of a transfer gate transistor, or defined on a top surface of a polysilicon plug structure which in turn contacts the underlying source/drain region. After deposition of an interlevel dielectric (ILD), layer, an opening is formed in a first ILD layer exposing a portion of the top surface of the ruthenium seed layer. An electroless plating procedure is then employed to fill the opening in the ILD layer with a voidless platinum plug structure. A capacitor opening is then formed in a second ILD layer exposing the top surface of the platinum contact plug structure. After formation of silicon nitride spacers on the sides of the capacitor opening, a platinum storage node structure is formed in the capacitor opening, overlying and contacting the top surface of the underlying platinum contact plug structure. After deposition of a high dielectric constant (high k), layer, such as Ta
2
O
5
or BaTiO
3
, a platinum layer is deposited. A patterning procedures is then used to define a capacitor top plate structure, and a capacitor dielectric layer, resulting in an MIM capacitor structure comprised of an overlying platinum upper electrode structure, a high k capacitor dielectric layer, and an underlying platinum storage node structure, with the MIM capacitor structure located in the capacitor opening, overlying and contacting the platinum contact plug structure.
REFERENCES:
patent: 5789320 (1998-08-01), Andricacos et al.
patent: 6130449 (2000-10-01), Matsuoka et al.
patent: 6153460 (2000-11-01), Ohnishi et al.
patent: 6159793 (2000-12-01), Lou
patent: 6207524 (2001-03-01), Gutsche
patent: 6235579 (2001-05-01), Lou
patent: 6274424 (2001-08-01), White
patent: 6313031 (2001-11-01), Schuele et al.
Ackerman Stephen B.
Ghyka Alexander
Saile George O.
Taiwan Semiconductor Manufacturing Company
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